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ds07-13722-8e fujitsu semiconductor data sheet copyright?2002-2006 fujitsu limited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 16-bit proprietary microcontroller cmos f 2 mc-16lx MB90480/485 series mb90f481/f482/487b/488b/483c mb90f488b/f489b/v480/v485b description the MB90480/485 series is a 16-bit general-purpose fujitsu microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing. the f 2 mc-16lx cpu core instruction set retains the at architecture of the f 2 mc* 1 family, with additional instruc- tions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. in addition, a 32-bit accumulato r is provided to enable long-word processing. the MB90480/485 series features embedded peripheral resources including 8/16-bit ppg, expanded i/o serial interface, uart, 10-bit a/d converter, 16-bit i/o timer, 8/16-bit up/down-counter, pwc timer, i 2 c* 2 interface, dtp/ external interrupt, chip sele ct, and 16-bit reload timer. *1 : f 2 mc is the abbreviation for fujitsu flexible microcontroller. *2 : purchase of fujitsu i 2 c components conveys a lic ense under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard a specification as defined by philips. features clock minimum instruction execution time: 40.0 ns/6.25 mhz base frequency multiplied 4 (25 mhz internal operating frequency/3.3 v 0.3 v) 62.5 ns/4 mhz base frequency multiplied 4 (16 mhz internal operating frequency/3.0 v 0.3 v) pll clock multiplier maximum memory space: 16 mbytes (continued)
MB90480/485 series 2 (continued) instruction set optimized for controller applications supported data types (bit, byte, word, or long word) typical addressing modes (23 types) 32-bit accumulator for enhanced high-precision calculation enhanced signed multiplication/division inst ruction and reti instruction functions instruction set designed for high-level pr ogramming language (c) and multi-task operations system stack pointer adopted instruction set symmetry and barrel shift instructions non-multiplex bus/multiplex bus compatible enhanced execution speed 4-byte instruction queue enhanced interrupt functions 8 levels setting with programmable priority, 8 external interrupts data transfer function ( dmac) up to 16 channels embedded rom flash versions : 192 kbytes, 256 kbytes, 384 kbytes, mask versions : 192 kbytes, 256 kbytes embedded ram flash versions : 4 kbytes, 6 kbytes, 10 kbytes , 24 kbytes, mask versions : 10 kbytes, 16 kbytes general purpose ports up to 84 ports (includes 16 ports with input pull-up resistance settings, 16 ports with ou tput open-drain settings) a/d converter 8-channel rc sequential comparison type (10-bit resolution, 3.68 s conversion time (at 25 mhz) ) i 2 c interface (mb90485 series on ly) : 1channel, p76/p77 n-ch open drain pin (without p-ch) do not apply high voltage in exce ss of recommended operating ranges to the n-ch open drain pin (with p-ch) in mb90v485b. pg (mb90485 series only) : 1 channel uart : 1 channel extended i/o serial inte rface (sio) : 2 channels 8/16-bit ppg : 3 channels (with 8-bit 6 channel/16-bit 3 channel mode switching function) 8/16-bit up/down counter/timer: 1 channel (with 8-bit 2 channels/16-bit 1-channel mode switching function) pwc (mb90485 series only) : 3 channels (capable of compare t he inputs to two of the three) 3 v/5 v i/f pin (mb90485 series only) p20 to p27, p30 to p37, p40 to p47, p70 to p77 16-bit reload timer : 1 channel 16-bit i/o timer : 2 channels input capture, 6 ch annels output compare, 1 channel free run timer on chip dual clock generator system low-power consumption mode with stop mode, sleep mode, cpu intermittent operation mode, watch mode, timebase timer mode packages : qfp 100/lqfp 100 process : cmos technology power supply voltage : 3 v, single power supply (s ome ports can be operated by 5 v power supply at mb90485 series)
MB90480/485 series 3 product lineup ? MB90480 series *1 : user pin : p20 to p27, p30 to p37, p40 to p47, p70 to p77 *2 : it is setting of jumper switch (t ool vcc) when emulator (mb2147-01) is used. please refer to the mb2147-01 or mb2147-20 hardware manual (3.3 emulator-dedicated power supply switching) about details. note : ensure that you must write to flash at v cc = 3.13 v to 3.60 v (3.3 v + 10 % , ? 5 % ) . mb90f481 mb90f482 mb90v480 classification flash memory product evaluation product rom size 192 kbytes 256 kbytes ? ram size 4 kbytes 6 kbytes 16 kbytes cpu function number of instructions : 351 instruction bit length : 8-bit, 16-bit instruction length : 1 byte to 7 bytes data bit length : 1-bit, 8-bit, 16-bit minimum instruction execution time : 40 ns (25 mhz machine clock) ports general-purpose i/o ports: up to 84 general-purpose i/o ports (cmos output) general-purpose i/o ports (w ith pull-up resistance) general-purpose i/o ports (n-ch open drain output) uart 1 channel, start-stop synchronized 8/16-bit ppg 8-bit 6 channels/16-bit 3 channels 8/16-bit up/down counter/timer event input pins : 6, 8-bit up/down counters : 2 8-bit reload/compare registers : 2 16-bit i/o timers 16-bit free run timer number of channels : 1 overflow interrupt output compare (ocu) number of channels : 6 pin input factor : a match signal of compare register input capture (icu) number of channels : 2 rewriting a register value upon a pin input (rising, falling, or both edges) dtp/external interrupt circuit number of external interrupt pin channels : 8 (edge or level detection) extended i/o serial in terface embedded 2 channels timebase timer 18-bit counter interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms , 131.1 ms (at 4 mhz base oscillator) a/d converter conversion resolution : 8/10-bit, switchable one-shot conversion mode (converts selected channel 1 time only) scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) continuous conversion mode (repeated conversion of selected channels) stop conversion mode (conversion of selected channels with repeated pause) watchdog timer reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 mhz base oscillator) low-power consumption (standby) modes stop mode, sleep mode, cpu intermitt ent operation mode, watch timer mode, timebase timer mode process cmos type not included security function user pin* 1 , 3 v/5 v versions emulator power supply* 2 ? included part number item
MB90480/485 series 4 ? mb90485 series (continued) mb90487b mb90488b mb90f488b mb90v485b mb90f489b mb90483c classification mask rom product flash memory product evaluation product flash memory product mask rom product rom size 192 kbytes 256 kbytes 256 kbytes ? 384 kbytes 256 kbytes ram size 10 kbytes 10 kbytes 10 kbytes 16 kbytes 24 kbytes 16 kbytes cpu function number of instructions : 351 instruction bit length : 8-bit, 16-bit instruction length : 1 byte to 7 bytes data bit length : 1-bit, 8-bit, 16-bit minimum instruction execution time : 40 ns (25 mhz machine clock) ports general-purpose i/o ports : up to 84 general-purpose i/o ports (cmos output) general-purpose i/o ports (with pull-up resistance) general-purpose i/o ports (n-ch open drain output) uart 1 channel, start-stop synchronized 8/16-bit ppg 8-bit 6 channels/16-bit 3 channels 8/16-bit up/down counter/timer event input pins : 6, 8-bit up/down counters : 2 8-bit reload/compare registers : 2 16-bit i/o timers 16-bit free run timer number of channels : 1 overflow interrupt output compare (ocu) number of channels : 6 pin input factor: a match signal of compare register input capture (icu) number of channels : 2 rewriting a register value upon a pin input (rising, falling, or both edges) dtp/external interrupt circuit number of external interrupt pin channels: 8 (edge or level detection) extended i/o serial interface embedded 2 channels i 2 c interface* 2 1 channel pg 1 channel pwc 3 channels timebase timer 18-bit counter interrupt cycles : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 mhz base oscillator) a/d converter conversion resolution : 8/10-bit, switchable one-shot conversion mode (convert s selected channel 1 time only) scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) continuous conversion mode (repeated conversion of selected channels) stop conversion mode (conversion of selected channels with repeated pause) part number item
MB90480/485 series 5 (continued) *1 : 3 v/5 v i/f pin : all pins should be for 3 v power supply without p20 to p27, p 30 to p37, p40 to p47, and p70 to p77. *2 : p76/p77 pins are n-ch open drai n pins (without p-ch) at built-in i 2 c. however, mb90v485b uses the n-ch open drain pin (with p-ch) . *3 : it is setting of jumper switch (too l vcc) when emulator (mb2147-01) is used. please refer to the mb2147-01 or mb2147-20 hardwar e manual (3.3 emulator-dedicated power supply switching) about details. notes : ? as for mb90v485b, input pins (pwc0, pw c1, pwc2/extc/scl and sda pins) for pwc/ pg/i 2 c become cmos input. ? ensure that you must write to flash at v cc = 3.13 v to 3.60 v (3.3 v + 10 % , ? 5 % ) . mb90487b mb90488b mb90f488b mb90v485b mb90f489b mb90483c watchdog timer reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 mhz base oscillator) low-power consumption (standby) modes stop mode, sleep mode, cpu intermittent o peration mode, watch timer mode, timebase timer mode process cmos type 3 v/5 v power supply* 1 3 v/5 v power supply* 1 3 v/5 v power supply* 1 included security function 3 v/5 v power supply* 1 3 v/5 v power supply* 1 included security function 3 v/5 v power supply* 1 emulator power supply* 3 ?? ? included ?? part number item
MB90480/485 series 6 pin assignment (top view) (fpt-100p-m06) 1 p20/a16 p21/a17 p22/a18 p23/a19 p24/a20/ppg0 p25/a21/ppg1 p26/a22/ppg2 p27/a23/ppg3 p30/a00/ain0 p31/a01/bin0 v ss p32/a02/zin0 p33/a03/ain1 p34/a04/bin1 p35/a05/zin1 p36/a06/pwc0* p37/a07/pwc1* p40/a08/sin2 p41/a09/sot2 p42/a10/sck2 p43/a11/mt00* p44/a12/mt01* v cc 5 p45/a13/extc* p46/a14/out4 p47/a15/out5 p70/sin0 p71/sot0 p72/sck0 p73/tin0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x0a x1a p57/clk rst p56/rdy p55/hak p54/hrq p53/wrh p52/wrl p51/rd p50/ale pa3/out3 pa2/out2 pa1/out1 pa0/out0 p97/in1 p96/in0 p95/ppg5 p94/ppg4 p93/frck/adtg/cs3 p92/sck1/cs2 p91/sot1/cs1 p90/sin1/cs0 p87/irq7 p86/irq6 p85/irq5 p84/irq4 p83/irq3 p82/irq2 md2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 p74/tot0 p75/pwc2* p76/scl* p77/sda* av cc avrh av ss p60/an0 p61/an1 p62/an2 p63/an3 vss p64/an4 p65/an5 p66/an6 p67/an7 p80/irq0 p81/irq1 md0 md1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p17/ad15/d15 p16/ad14/d14 p15/ad13/d13 p14/ad12/d12 p13/ad11/d11 p12/ad10/d10 p11/ad09/d09 p10/ad08/d08 p07/ad07/d07 p06/ad06/d06 p05/ad05/d05 p04/ad04/d04 p03/ad03/d03 p02/ad02/d02 p01/ad01/d01 p00/ad00/d00 v cc 3 x1 x0 v ss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 * : these are the pins for mb90485 series. the pins for MB90480 series are p36/a06, p37/a07, p43/a11, p44/a12, p45/a13, p75 to p77. note : mb90485 series only ? i 2 c pin p77 and p76 are n-ch open drain pin (w ithout p-ch) . however, mb90v485b uses the n-ch open drain pin (with p-ch) . ? p20 to p27, p30 to p37, p40 to p47 and p70 to p77 are also used as 3 v/5 v i/f pin. ? as for mb90v485b, input pins (pwc0, pwc1, pwc2/extc/scl and sda pins) for pwc/ pg/i 2 c become cmos input.
MB90480/485 series 7 (top view) (fpt-100p-m05) 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 r s t p56/rdy p55/hak p54/hrq p5 3 /wrh p52/wrl p51/rd p50/ale pa 3 /out 3 pa2/out2 pa1/out1 pa0/out0 p97/in1 p96/in0 p95/ppg5 p94/ppg4 p9 3 /frck/adtg/c s3 p92/ s ck1/c s 2 p91/ s ot1/c s 1 p90/ s in1/c s 0 p 8 7/irq7 p 8 6/irq6 p 8 5/irq5 p 8 4/irq4 p 83 /irq 3 75 74 7 3 72 71 70 69 6 8 67 66 65 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 p22/a1 8 p2 3 /a19 p24/a20/ppg0 p25/a21/ppg1 p26/a22/ppg2 p27/a2 3 /ppg 3 p 3 0/a00/ain0 p 3 1/a01/bin0 v ss p 3 2/a02/zin0 p 33 /a0 3 /ain1 p 3 4/a04/bin1 p 3 5/a05/zin1 p 3 6/a06/pwc0 * p 3 7/a07/pwc1 * p40/a0 8 / s in2 p41/a09/ s ot2 p42/a10/ s ck2 p4 3 /a11/mt00 * p44/a12/mt01 * v cc 5 p45/a1 3 /extc * p46/a14/out4 p47/a15/out5 p70/ s in0 p71/ s ot0 p72/ s ck0 p7 3 /tin0 p74/tot0 p75/pwc2 * p76/ s cl * p77/ s da * av cc avrh av ss p60/an0 p61/an1 p62/an2 p6 3 /an 3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p 8 0/irq0 p 8 1/irq1 md0 md1 md2 p 8 2/irq2 p21/a17 p20/a16 p17/ad15/d15 p16/ad14/d14 p15/ad1 3 /d1 3 p14/ad12/d12 p1 3 /ad11/d11 p12/ad10/d10 p11/ad09/d09 p10/ad0 8 /d0 8 p07/ad07/d07 p06/ad06/d06 p05/ad05/d05 p04/ad04/d04 p0 3 /ad0 3 /d0 3 p02/ad02/d02 p01/ad01/d01 p00/ad00/d00 v cc 3 x1 x0 v ss x0a x1a p57/clk 26 27 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 100 99 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 8 0 79 7 8 77 76 * : these are the pins for mb90485 series. the pins for MB90480 series are p36/a06, p37/a07, p43/ a11, p44/a12, p45/a13, p75 to p77. note : mb90485 series only ? i 2 c pin p77 and p76 are n-ch open drain pin (without p-ch) . however, mb90v485b uses the n-ch open drain pin (with p-ch) . ? p20 to p27, p30 to p37, p40 to p47 and p 70 to p77 are also used as 3 v/5 v i/f pin. ? as for mb90v485b, input pins (pwc0, pwc1 , pwc2/extc/scl and sda pins) for pwc/ pg/i 2 c become cmos input.
MB90480/485 series 8 pin descriptions (continued) pin no. pin name i/o circuit type* 3 function qfp* 1 lqfp* 2 82 80 x0 a clock (oscillator) input pin 83 81 x1 a clock (oscillator) output pin 80 78 x0a a clock (32 khz oscillator) input pin 79 77 x1a a clock (32 khz oscillator) output pin 77 75 rst b reset input pin 85 to 92 83 to 90 p00 to p07 c (cmos) this is a general purpose i/o port. a setting in the port 0 input resistance register (rdr0) can be used to apply pull-up resistance (rd00-rd07 = ?1?) . (disabled when pin is set for output.) ad00 to ad07 in multiplex mode, these pins func tion as the external address/data bus low i/o pins. d00 to d07 in non-multiplex mode, these pins function as the external data bus low output pins. 93 to 100 91 to 98 p10 to p17 c (cmos) this is a general purpose i/o port. a setting in the port 1 input resistance register (rdr1) can be used to apply pull-up resistance (rd10-rd17 = ?1?) . (disabled when pin is set for output.) ad08 to ad15 in multiplex mode, these pins func tion as the external address/data bus high i/o pins. d08 to d15 in non-multiplex mode, these pins function as the external data bus high output pins. 1 to 4 99, 100, 1, 2 p20 to p23 e ( cmos / h ) this is a general purpose i/o port. w hen the bits of external address output control register (hacr) are set to "1" in external bus mode, these pins function as general purpose i/o ports. a16 to a19 when the bits of external address ou tput control register (hacr) are set to "0" in multiplex mode, thes e pins function as address high output pins (a16-a19). when the bits of external address ou tput control register (hacr) are set to "0" in non-multiplex mode, these pins function as address high output pins (a16-a19). 5 to 8 3 to 6 p24 to p27 e ( cmos / h ) this is a general purpose i/o port. w hen the bits of external address output control register (hacr) are set to "1" in external bus mode, these pins function as general purpose i/o ports. a20 to a23 when the bits of external address ou tput control register (hacr) are set to "0" in multiplex mode, thes e pins function as address high output pins (a20-a23). when the bits of external address ou tput control register (hacr) are set to "0" in non-multiplex mode, these pins function as address high output pins (a20-a23). ppg0 to ppg3 output pins for ppg. 97 p30 e ( cmos / h ) this is a general purpose i/o port. a00 in non-multiplex mode, this pin functions as an external address pin. ain0 8/16-bit up/down timer input pin (ch.0) .
MB90480/485 series 9 (continued) pin no. pin name i/o circuit type* 3 function qfp* 1 lqfp* 2 10 8 p31 e ( cmos / h ) this is a general purpose i/o port. a01 in non-multiplex mode, this pin f unctions as an external address pin. bin0 8/16-bit up/down timer input pin (ch.0) . 12 10 p32 e ( cmos / h ) this is a general purpose i/o port. a02 in non-multiplex mode, this pin f unctions as an external address pin. zin0 8/16-bit up/down timer input pin (ch.0) 13 11 p33 e ( cmos / h ) this is a general purpose i/o port. a03 in non-multiplex mode, this pin f unctions as an external address pin. ain1 8/16-bit up/down timer input pin (ch.1) . 14 12 p34 e ( cmos / h ) this is a general purpose i/o port. a04 in non-multiplex mode, this pin f unctions as an external address pin. bin1 8/16-bit up/down timer input pin (ch.1) . 15 13 p35 e ( cmos / h ) this is a general purpose i/o port. a05 in non-multiplex mode, this pin f unctions as an external address pin. zin1 8/16-bit up/down timer input pin (ch.1) 16, 17 14, 15 p36, p37 d (cmos) MB90480 series this is a general purpose i/o port. a06, a07 in non-multiplex mode, this pin functions as an external address pin. p36, p37 e ( cmos / h ) mb90485 series this is a general purpose i/o port. a06, a07 in non-multiplex mode, this pin functions as an external address pin. pwc0, pwc1* 4 this is a pwc input pin. 18 16 p40 g ( cmos / h ) this is a general purpose i/o port. a08 in non-multiplex mode, this pin f unctions as an external address pin. sin2 extended i/o serial interface input pin. 19 17 p41 f (cmos) this is a general purpose i/o port. a09 in non-multiplex mode, this pin f unctions as an external address pin. sot2 extended i/o serial interface output pin. 20 18 p42 g ( cmos / h ) this is a general purpose i/o port. a10 in non-multiplex mode, this pin f unctions as an external address pin. sck2 extended i/o serial interf ace clock input/output pin.
MB90480/485 series 10 (continued) pin no. pin name i/o circuit type* 3 function qfp* 1 lqfp* 2 21, 22 19, 20 p43, p44 f (cmos) MB90480 series this is a general purpose i/o port. a11, a12 in non-multiplex mode, this pin functions as an external address pin. p43, p44 f (cmos) mb90485 series this is a general purpose i/o port. a11, a12 in non-multiplex mode, this pin functions as an external address pin. mt00, mt01 pg output pin. 24 22 p45 f (cmos) MB90480 series this is a general purpose i/o port. a13 in non-multiplex mode, this pin functions as an external address pin. p45 g ( cmos/h ) mb90485 series this is a general purpose i/o port. a13 in non-multiplex mode, this pin functions as an external address pin. extc* 4 pg input pin. 25, 26 23, 24 p46, p47 f (cmos) this is a general purpose i/o port. a14, a15 in non-multiplex mode, this pin functions as an external address pin. out4/ out5 output compare event output pins. 70 68 p50 d (cmos) this is a general purpose i/o port . in external bus mode, this pin functions as the ale pin. ale in external bus mode, this pin functions as the address load enable (ale) signal pin. 71 69 p51 d (cmos) this is a general purpose i/o port . in external bus mode, this pin functions as the rd pin. rd in external bus mode, this pin func tions as the read strobe output (rd ) signal pin. 72 70 p52 d (cmos) this is a general purpose i/o port. in external bus mode, when the wre bit in the epcr register is set to ?1?, this pin functions as the wrl pin. wrl in external bus mode, this pin functi ons as the lower data write strobe output (wrl ) pin. when the wre bit in the epcr register is set to ?0?, this pin functions as a general purpose i/o port. 73 71 p53 d (cmos) this is a general purpose i/o port. in external bus mode with 16-bit bus width, when the wre bit in the epcr register is set to ?1?, this pin functions as the wrh pin. wrh in external bus mode with 16-bit bus width, this pin functions as the upper data write strobe output (wrh ) pin. when the wre bit in the epcr register is set to ?0?, this pin functions as a general purpose i/o port.
MB90480/485 series 11 (continued) pin no. pin name i/o circuit type* 3 function qfp* 1 lqfp* 2 74 72 p54 d (cmos) this is a general purpose i/o port. in external bus mode, when the hde bit in the epcr register is set to ?1?, this pin functions as the hrq pin. hrq in external bus mode, this pin f unctions as the hold request input (hrq) pin. when the hde bit in the ep cr register is set to ?0?, this pin functions as a general purpose i/o port. 75 73 p55 d (cmos) this is a general purpose i/o port. in external bus mode, when the hde bit in the epcr register is set to ?1?, this pin functions as the hak pin. hak in external bus mode, this pin func tions as the hold acknowledge out- put (hak ) pin. when the hde bit in the epc r register is set to ?0?, this pin functions as a general purpose i/o port. 76 74 p56 d (cmos) this is a general purpose i/o port. in external bus mode, when the rye bit in the epcr register is set to ?1?, this pin functions as the rdy pin. rdy in external bus mode, this pin func tions as the external ready (rdy) input pin. when the rye bit in the epcr register is set to ?0?, this pin functions as a general purpose i/o port. 78 76 p57 d (cmos) this is a general purpose i/o port. in external bus mode, when the cke bit in the epcr register is set to ?1?, this pin functions as the clk pin. clk in external bus mode, this pin f unctions as the machine cycle clock (clk) output pin. when the cke bi t in the epcr register is set to ?0?, this pin functions as a general purpose i/o port. 38 to 41 36 to 39 p60 to p63 h (cmos) these are general purpose i/o ports. an0 to an3 these are the analog input pins for a/d converter. 43 to 46 41 to 44 p64 to p67 h (cmos) these are general purpose i/o ports. an4 to an7 these are the analog input pins for a/d converter. 27 25 p70 g ( cmos / h ) this is a general purpose i/o port. sin0 this is the uart serial data input pin. 28 26 p71 f (cmos) this is a general purpose i/o port. sot0 this is the uart serial data output pin. 29 27 p72 g ( cmos / h ) this is a general purpose i/o port. sck0 this is the uart serial communication clock i/o pin. 30 28 p73 g ( cmos / h ) this is a general purpose i/o port. tin0 this is the 16-bit reload timer event input pin. 31 29 p74 f (cmos) this is a general purpose i/o port. tot0 this is the 16-bit reload timer output pin.
MB90480/485 series 12 (continued) pin no. pin name i/o circuit type* 3 function qfp* 1 lqfp* 2 32 30 p75 f (cmos) MB90480 series this is a general purpose i/o port. p75 g ( cmos / h ) mb90485 series this is a general purpose i/o port. pwc2* 4 this is a pwc input pin. 33 31 p76 f (cmos) MB90480 series this is a general purpose i/o port. p76 i (nmos/h) mb90485 series this is a general purpose i/o port. scl* 4 serves as the i 2 c interface data i/o pin. during opera- tion of the i 2 c interface, leave the port output in a high impedance state. 34 32 p77 f (cmos) MB90480 series this is a general purpose i/o port. p77 i (nmos/h) mb90485 series this is a general purpose i/o port. sda* 4 serves as the i 2 c interface data i/o pin. during opera- tion of the i 2 c interface, leave the port output in a high impedance state. 47, 48 45, 46 p80, p81 e ( cmos / h ) these are general purpose i/o ports. irq0, irq1 external interrupt input pins. 52 to 57 50 to 55 p82 to p87 e ( cmos / h ) these are general purpose i/o ports. irq2 to irq7 external interrupt input pins. 58 56 p90 e ( cmos / h ) this is a general purpose i/o port. sin1 extended i/o serial interface data input pin. cs0 chip select 0. 59 57 p91 d (cmos) this is a general purpose i/o port. sot1 extended i/o serial interface data output pin. cs1 chip select 1. 60 58 p92 e ( cmos / h ) this is a general purpose i/o port. sck1 extended i/o serial interface clock input/output pin. cs2 chip select 2. 61 59 p93 e ( cmos / h ) this is a general purpose i/o port. frck when the free run timer is in use, this pin functions as the external clock input pin. adtg when the a/d converter is in use, this pin functions as the external trigger input pin. cs3 chip select 3. 62 60 p94 d (cmos) this is a general purpose i/o port. ppg4 ppg timer output pin.
MB90480/485 series 13 (continued) *1 : qfp : fpt-100p-m06 *2 : lqfp : fpt-100p-m05 *3 : for the i/o circuit type, refer to ? i/o circuit types?. *4 : as for mb90v485b, input pins become cmos input. pin no. pin name i/o circuit type* 3 function qfp* 1 lqfp* 2 63 61 p95 d (cmos) this is a general purpose i/o port. ppg5 ppg timer output pin. 64 62 p96 e ( cmos / h ) this is a general purpose i/o port. in0 input capture ch.0 trigger input pin. 65 63 p97 e ( cmos / h ) this is a general purpose i/o port. in1 input capture ch.1 trigger input pin. 66 to 69 64 to 67 pa0 to pa3 d (cmos) these are general purpose i/o ports. out0 to out3 output compare event output pins. 35 33 av cc ? a/d converter analog power supply input pin. 36 34 avrh ? a/d converter reference voltage input pin. 37 35 av ss ? a/d converter gnd pin. 49 to 51 47 to 49 md0 to md2 j ( cmos / h ) operating mode selection input pins. 84 82 v cc 3 ? 3.3 v 0.3 v power supply pins (v cc 3) . 23 21 v cc 5 ? MB90480 series 3.3 v 0.3 v power supply pin. usually, use v cc = v cc 3 = v cc 5 as a 3 v power supply. mb90485 series 3 v/5 v power supply pin. 5 v power supply pin when p20 to p27, p30 to p37, p40 to p47, p70 to p77 are used as 5 v i/f pins. usually, use v cc = v cc 3 = v cc 5 as a 3 v power supply (when the 3 v power supply is used alone) . 11, 42, 81 9, 40, 79 v ss ? gnd pins.
MB90480/485 series 14 i/o circuit types (continued) type circuit remarks a feedback resistance x1, x0 : approx. 1 m ? x1a, x0a : approx. 10 m ? with standby control b hysteresis input with pull-up resistance c with input pull-up resistance control cmos level input/output d cmos level input/output e hysteresis input cmos level output x1, x1a x0, x0a standby control signal hysteresis input ctl cmos p-ch p-ch n-ch cmos p-ch n-ch cmos p-ch n-ch
MB90480/485 series 15 (continued) type circuit remarks f cmos level input/output with open drain control g cmos level output hysteresis input with open drain control h cmos level input/output analog input i hysteresis input n-ch open drain output j (flash memory product) cmos level input with high voltage control for flash testing (mask rom product) hysteresis input cmos p-ch n-ch open drain control signal p-ch n-ch open drain control signal hysteresis input cmos p-ch n-ch analog input n-ch digital output control signal mode input diffusion resistance (flash memory product) hysteresis input (mask rom product)
MB90480/485 series 16 handling devices 1. be careful never to exceed maximum rated voltages (preventing latch-up) in cmos ic devices, a condition known as latch-up may occur if voltages higher than v cc or lower than v ss are applied to input or output pins other than medium-o r high-voltage pins, or if the voltage applied between v cc and v ss pins exceeds the rated voltage level. when latch-up occurs, the power supply current increa ses rapidly causing the pos sibility of thermal damage to circuit elements. therefore it is necessary to ensure th at maximum ratings are not exceeded in circuit operation. similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (av cc and avrh) and analog input voltages do not exceed the digital power supply (v cc ) . 2. treatment of unused pins leaving unused input pins unconnect ed can cause abnormal operation or latch-up, leading to permanent damage. unused input pins should always be pulled up or down through resistance of at least 2 k ? . any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. 3. treatment of power supply pins (v cc /v ss ) when multiple v cc /v ss pins are present, device design considerat ions for prevention of latch-up and unwanted electromagnetic interference, abnormal strobe signal operation due to ground level rise, and conformity with total output current ratings require that all power suppl y pins must be externally connected to power supply or ground. consideration should be given to connec ting power supply sources to the v cc /v ss pins of this device with as low impedance as possible. it is also recommended th at a bypass capacitor of approximately 0.1 f be placed between the v cc and v ss lines as close to this device as possible. 4. crystal oscillator circuits noise around the x0/x1, or x0a/x1a pins may cause this device to operate abnormally. in the interest of stable operation it is strongly recommended that printed circui t board artwork places ground bypass capacitors as close as possible to the x0/x1, x0a/x1 a and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits. 5. precautions when turning the power supply on in order to prevent abnormal operation in the chip?s intern al step-down circuits, a voltage rise time during power- on of 50 s (0.2 v to 2.7 v) or greater should be assured. 6. supply voltage stabilization even within the operating range of v cc supply voltage, rapid voltage fluctu ations may cause abnormal operation. as a standard for power supply voltage stability, it is recommended that the peak-to-peak v cc ripple voltage at commercial supply frequency (50 mhz to 60 mhz) be 10 % o r le ss of v cc , and that the transient voltage fluctuation be no more than 0.1 v/ms or less wh en the power supply is turned on or off. 7. proper power-on/off sequence the a/d converter power (av cc , avrh) and analog input (an0 to an7) mu st be turned on afte r the digital power supply (v cc ) is turned on. the a/d converter power (av cc , avrh) and analog input (an0 to an7) must be shut off before the digital power supply (v cc ) is shut off. care should be taken that avrh does not exceed av cc . even when pins used as analog input pins are doubled as input ports, be sure that the in put voltage does not exceed av cc .
MB90480/485 series 17 8. treatment of power supply pins on models with a/d converters even when the a/d converters are not in use, be sure to make the necessary connections av cc = avrh = v cc , and av ss = v ss . 9. notes on using power supply only the mb90485 series usually uses a 3 v power supply. by setting v cc 3 = 3 v power supply and v cc 5 = 5 v power supply, p20 to p27, p30 to p37, p40 to p47 and p70 to p77 can be interfaced as 5 v power supplies separately from the main 3 v power supply. note that the analog power supplies (such as av cc and av ss ) for the a/d converter can be used only as 3 v power supplies. 10. notes on using external clock even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. when us ing an external clock, 25 mhz should be the upper frequency limit. the following figure shows a sample use of external clock signals. 11. treatment of nc pins nc (internally connected) pins should always be left open. 12. notes on during operation of pll clock mode on this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the pll clock mode is selected, a self-oscillator circuit contained in the pll may c ontinue its operation at its self-running frequency. however, fujitsu will not guar antee results of operation if such failure occurs. 13. when the MB90480/485 series microcontroller is used as a single system when the MB90480/485 series microcon troller is used as a single sy stem, use connections so the x0a = v ss , and x1a = open. 14. writing to flash memory for writing to flash memory, always ensure that the operating voltage v cc is between 3.0 v and 3.6 v. x0 x1 open
MB90480/485 series 18 block diagram ram rom dmac 8 2 x0, x1, r s t x0a, x1a md2, md1, md0 s in0 s ot0 s ck0 s in1, s in2 s ot1, s ot 2 s ck1, s ck2 av cc avrh av ss adtg an0 to an7 ain0, ain1 bin0, bin1 zin0, zin1 ppg0, ppg1 ppg2, ppg 3 ppg4, ppg5 888888888 p00 p07 p10 p17 p20 p27 p 3 0 p 3 7 p40 p47 p50 p57 p60 p67 p70 p77 p 8 0 p 8 7 8 p90 p97 4 pa 0 pa 3 in0, in1 out0, out1, out2, out 3 , out4, out5 c s 0, c s 1, c s 2, c s3 tin0 tot0 irq0 to irq7 8 s cl s da extc mt00 mt01 pwc0 pwc1 pwc2 clock control circ u it cpu f 2 mc16lx s erie s core interr u pt controller 8 /16- b it ppg 8 /16- b it u p/down co u nter/timer pg chip s elect inp u t/o u tp u t timer 16- b it inp u t c a pt u re 2 ch a nnel s 16- b it o u tp u t comp a re 6 ch a nnel s 16- b it free-r u n timer 16- b it relo a d timer i 2 c interf a ce extern a l interr u pt uart extended i/o s eri a l interf a ce 2 ch a nnel s a/d converter ( 10- b it ) pwc 3 ch a nnel s i/o port to to to to to to to to to to to comm u nic a tion pre s c a ler f 2 mc-16lx b us : only mb904 8 5 s erie s p00 to p07 (8 pins) : with an input pull-up resistance setting register. p10 to p17 (8 pins) : with an input pull-up resistance setting register. p40 to p47 (8 pins) : with an open drain setting register. p70 to p77 (8 pins) : with an open drain setting register. mb90485 series only ? i 2 c pin p77 and p76 are n-ch open drain pin (w ithout p-ch) . however, mb90v485b uses the n-ch open drain pin (with p-ch) . ? p20 to p27, p30 to p37, p 40 to p47 and p70 to p77 are also used as 3 v/5 v i/f pin. ? as for mb90v485b, input pins (pwc0, pw c1, pwc2/extc/scl and sda pins) for pwc/ pg/i 2 c become cmos input. note : in the above diagram, i/o ports share in ternal function blocks and pins. however, when a set of pins is used with an internal modul e, it cannot also be used as an i/o port.
MB90480/485 series 19 memory map mb90f481/f482/487b/488b/483c/f488b/v480/v485b/f489b *1 : no memory cells from fc0000 h to fc7fff h and fe0000 h to fe7fff h . the upper part of the 00 bank is set up to mirror the image of ff bank rom, to enable efficient use of small model c compilers. because the lower 16-bit address of th e ff bank and the lower 16 -bit address of the 00 bank are the same, enabling reference to tables in ro m without using the for specification in the pointer declaration. for example, in accessing address 00c000 h it is actually the contents of rom at ffc000 h that are accessed. if the ms bit in the romm register is set to ?0?, th e rom area in the ff bank will exceed 48 kbytes and it is not possible to reflect the entire area in the im age in the 00 bank. therefore the image from ff4000 h to ffffff h is reflected in the 00 b ank and the area from ff0000 h to ff3fff h can be seen in the ff bank only. (continued) model address #1 address #2 address #3 mb90f481 fc0000 h * 1 004000 h or 008000 h , selected by the ms bit in the romm register 001100 h mb90f482 fc0000 h 001900 h mb90487b fd0000 h 002900 h mb90488b fc0000 h 002900 h mb90f488b fc0000 h 002900 h mb90v480 (fc0000 h ) 004000 h mb90v485b (fc0000 h ) 004000 h mb90483c fb0000 h * 4 004000 h mb90f489b f90000 h * 2 0080000 h fixed 006100 h * 3 ffffff h 010000 h 000100 h 0000d0 h 000000 h ram ? ram ram rom a re a rom a re a rom a re a ff ba nk im a ge rom a re a ff ba nk im a ge peripher a l peripher a l peripher a l s ingle chip intern a l rom extern a l bus extern a l rom extern a l bus address #1 address #3 register : internal : external : access inhibited address #2 * : in models where address #3 overlaps with address #2, this external area does not exist. register register
MB90480/485 series 20 (continued) *2 : in mb90f489b, there is no acce ss to f8 bank and fc bank on the single-chip mode or the internal-rom external-bus mode. *3 : because installed-ram area is larger than mb90 v485b, mb90f489b should execute emulation in an area that is larger than 004000 h by the emulation memory area setting on the tool side. *4 : in mb90483c, there is no access to f8 bank to fa bank and fc bank on the single-chip mode or the internal- rom external-bus mode.
MB90480/485 series 21 mb90f489b ram ffffff h ff0000 h feffff h fdffff h fe0000 h fcffff h fd0000 h fbffff h fc0000 h fb0000 h faffff h f9ffff h fa0000 h f90000 h f 8 ffff h f 8 0000 h f7ffff h 010000 h 00ffff h 00 8 000 h 007fff h 006100 h 0060ff h 000100 h 0000ff h 0000d0 h 0000cf h 000000 h ram ram peripher a l peripher a l peripher a l regi s ter regi s ter regi s ter rom (fb ba nk) rom (fa ba nk) rom (f9 ba nk) rom (fb ba nk) rom (fa ba nk) rom (f9 ba nk) s ingle chip intern a l rom extern a l bus extern a l rom extern a l bus rom a re a ff ba nk im a ge rom a re a ff ba nk im a ge rom (fe ba nk) rom (ff ba nk) rom (fd ba nk) rom (fe ba nk) rom (ff ba nk) rom (fd ba nk) : intern a l : extern a l : acce ss inhi b ited
MB90480/485 series 22 mb90483c ram ffffff h ff0000 h feffff h fdffff h fe0000 h fcffff h fd0000 h fbffff h fc0000 h fb0000 h faffff h f9ffff h fa0000 h f90000 h f 8 ffff h f 8 0000 h f7ffff h 010000 h 00ffff h 004000 h 00 3 fff h 000100 h 0000ff h 0000d0 h 0000cf h 000000 h ram ram 004000 h 00 8 000 h or single chip internal rom external bus external rom external bus rom (ff bank) rom (ff bank) register peripheral peripheral peripheral : internal : external : access inhibited register register rom area ff bank image rom area ff bank image rom (fe bank) rom (fe bank) rom (fd bank) rom (fd bank) rom (fb bank) rom (fb bank)
MB90480/485 series 23 f 2 mc-16l cpu programming model dedicated registers general purpose registers processor status ah al dpr pcb dtb usb ssb adb 8-bit 16-bit 32-bit usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register r1 r0 r3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw3 16-bit 000180 h + rp 10 h rw4 rw5 rw6 rw7 rl0 rl1 rl2 rl3 msb lsb ilm 15 13 ps rp ccr 12 8 70
MB90480/485 series 24 i/o map (continued) address register name abbreviated register name read/ write resource name initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 07 h port 7 data register pdr7 r/w port 7 xxxxxxxx b (MB90480 series) 11xxxxxx b (mb90485 series) 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx b 0a h port a data register pdra r/w port a ----xxxx b 0b h up/down timer input enable register udre r/w up/down timer input control xx000000 b 0c h interrupt/dtp enable register enir r/w dtp/external interrupts 00000000 b 0d h interrupt/dtp source register eirr r/w xxxxxxxx b 0e h request level setting register elvr r/w 00000000 b 0f h request level setting register r/w 00000000 b 10 h port 0 direction register ddr0 r/w port 0 00000000 b 11 h port 1 direction register ddr1 r/w port 1 00000000 b 12 h port 2 direction register ddr2 r/w port 2 00000000 b 13 h port 3 direction register ddr3 r/w port 3 00000000 b 14 h port 4 direction register ddr4 r/w port 4 00000000 b 15 h port 5 direction register ddr5 r/w port 5 00000000 b 16 h port 6 direction register ddr6 r/w port 6 00000000 b 17 h port 7 direction register ddr7 r/w port 7 00000000 b (MB90480 series) xx000000 b (mb90485 series) 18 h port 8 direction register ddr8 r/w port 8 00000000 b 19 h port 9 direction register ddr9 r/w port 9 00000000 b 1a h port a direction register ddra r/w port a ----0000 b 1b h port 4 output pin register odr4 r/w port 4 (open-drain control) 00000000 b 1c h port 0 input resistance register rdr0 r/w port 0 (resistance control) 00000000 b 1d h port 1 input resistance register rdr1 r/w port 1 (resistance control) 00000000 b 1e h port 7 output pin register odr7 r/w port 7 (open-drain control) 00000000 b (MB90480 series) xx000000 b (mb90485 series) 1f h analog input enable register ader r/w port 6, a/d 11111111 b
MB90480/485 series 25 (continued) address register name abbreviated register name read/ write resource name initial value 20 h serial mode register smr r/w uart 00000x00 b 21 h serial control register scr w, r/w 00000100 b 22 h serial input/output register sidr/sodr r/w xxxxxxxx b 23 h serial status register ssr r, r/w 00001000 b 24 h (reserved area) 25 h communication prescaler control register cdcr r/w communication prescaler (uart) 00--0000 b 26 h serial mode control status register 0 smcs0 r/w sio1 (ch.0) ----0000 b 27 h 00000010 b 28 h serial data register 0 sdr0 r/w xxxxxxxx b 29 h communication prescaler control register 0 sdcr0 r/w communication prescaler sio1 (ch.0) 0---0000 b 2a h serial mode control status register 1 smcs1 r/w sio2 (ch.1) ----0000 b 2b h 00000010 b 2c h serial data register 1 sdr1 r/w xxxxxxxx b 2d h communication prescaler control register 1 sdcr1 r/w communication prescaler sio2 (ch.1) 0---0000 b 2e h reload register l (ch.0) ppll0 r/w 8/16-bit ppg (ch.0 to ch.5) xxxxxxxx b 2f h reload register h (ch.0) pplh0 r/w xxxxxxxx b 30 h reload register l (ch.1) ppll1 r/w xxxxxxxx b 31 h reload resister h (ch.1) pplh1 r/w xxxxxxxx b 32 h reload register l (ch.2) ppll2 r/w xxxxxxxx b 33 h reload register h (ch.2) pplh2 r/w xxxxxxxx b 34 h reload register l (ch.3) ppll3 r/w xxxxxxxx b 35 h reload register h (ch.3) pplh3 r/w xxxxxxxx b 36 h reload register l (ch.4) ppll4 r/w xxxxxxxx b 37 h reload register h (ch.4) pplh4 r/w xxxxxxxx b 38 h reload register l (ch.5) ppll5 r/w xxxxxxxx b 39 h reload register h (ch.5) pplh5 r/w xxxxxxxx b 3a h ppg0 operating mode control register ppgc0 r/w 0x000xx1 b 3b h ppg1 operating mode control register ppgc1 r/w 0x000001 b 3c h ppg2 operating mode control register ppgc2 r/w 0x000xx1 b 3d h ppg3 operating mode control register ppgc3 r/w 0x000001 b 3e h ppg4 operating mode control register ppgc4 r/w 0x000xx1 b 3f h ppg5 operating mode control register ppgc5 r/w 0x000001 b 40 h ppg0, ppg1 output control register ppg01 r/w 8/16-bit ppg 00000000 b 41 h (reserved area) 42 h ppg2, ppg3 output control register ppg23 r/w 8/16-bit ppg 00000000 b 43 h (reserved area)
MB90480/485 series 26 (continued) address register name abbre- viated register name read/ write resource name initial value 44 h ppg4, ppg5 output control regi ster ppg45 r/w 8/16-bit ppg 00000000 b 45 h (reserved area) 46 h control status register adcs1 r/w a/d converter 00000000 b 47 h adcs2 w, r/w 00000000 b 48 h data register adcr1 r xxxxxxxx b 49 h adcr2 w, r 00000xxx b 4a h output compare register (ch.0) lower digits occp0 r/w 16-bit input/output timer output compare (ch.0 to ch.5) 00000000 b 4b h output compare register (ch.0) upper digits 00000000 b 4c h output compare register (ch.1) lower digits occp1 r/w 00000000 b 4d h output compare register (ch.1) upper digits 00000000 b 4e h output compare register (ch.2) lower digits occp2 r/w 00000000 b 4f h output compare register (ch.2) upper digits 00000000 b 50 h output compare register (ch.3) lower digits occp3 r/w 00000000 b 51 h output compare register (ch.3) upper digits 00000000 b 52 h output compare register (ch.4) lower digits occp4 r/w 00000000 b 53 h output compare register (ch.4) upper digits 00000000 b 54 h output compare register (ch.5) lower digits occp5 r/w 00000000 b 55 h output compare register (ch.5) upper digits 00000000 b 56 h output control register (ch.0) ocs0 r/w 0000--00 b 57 h output control register (ch.1) ocs1 r/w ---00000 b 58 h output control register (ch.2) ocs2 r/w 0000--00 b 59 h output control register (ch.3) ocs3 r/w ---00000 b 5a h output control register (ch.4) ocs4 r/w 0000--00 b 5b h output control register (ch.5) ocs5 r/w ---00000 b 5c h input capture data register (ch.0) lower digits ipcp0 r 16-bit input/output timer input capture (ch.0, ch.1) xxxxxxxx b 5d h input capture data register (ch.0) upper digits r xxxxxxxx b 5e h input capture data register (ch.1) lower digits ipcp1 r xxxxxxxx b 5f h input capture data register (ch.1) upper digits r xxxxxxxx b 60 h input capture control status register ics01 r/w 00000000 b 61 h (reserved area)
MB90480/485 series 27 (continued) address register name abbreviated register name read/ write resource name initial value 62 h timer counter data register lower digits tcdt r/w 16-bit input/output timer free run timer 00000000 b 63 h timer counter data register upper digits tcdt r/w 00000000 b 64 h timer control status register tccs r/w 00000000 b 65 h timer control status register tccs r/w 0--00000 b 66 h compare clear register lower digits cpclr r/w xxxxxxxx b 67 h compare clear register upper digits xxxxxxxx b 68 h up/down count register (ch.0) udcr0 r 8/16-bit up/down 00000000 b 69 h up/down count register (ch.1) udcr1 r 00000000 b 6a h reload/compare register (ch.0) rcr0 w 00000000 b 6b h reload/compare register (ch.1) rcr1 w 00000000 b 6c h counter control register (ch.0) lower digits ccrl0 w, r/w 0x00x000 b 6d h counter control register (ch.0) upper digits ccrh0 r/w 00000000 b 6e h (reserved area) 6f h rom mirror function select register romm r/w rom mirroring function ------ + 1 b 70 h counter control register (ch.1) lower digits ccrl1 w, r/w 8/16-bit up/down 0x00x000 b 71 h counter control register (ch.1) upper digits ccrh1 r/w -0000000 b 72 h counter status register (ch.0) csr0 r, r/w 00000000 b 73 h (reserved area) 74 h counter status register (ch.1) csr1 r, r/w 8/16-bit udc 00000000 b 75 h (reserved area) 76 h * pwc control/status register pwcsr0 r, r/w pwc (ch.0) 00000000 b 77 h * 0000000x b 78 h * pwc data buffer register pwcr0 r/w 00000000 b 79 h * 00000000 b 7a h * pwc control/status register pwcsr1 r, r/w pwc (ch.1) 00000000 b 7b h * 0000000x b 7c h * pwc data buffer register pwcr1 r/w 00000000 b 7d h * 00000000 b 7e h * pwc control/status register pwcsr2 r, r/w pwc (ch.2) 00000000 b 7f h * 0000000x b 80 h * pwc data buffer register pwcr2 r/w 00000000 b 81 h * 00000000 b 82 h * dividing ratio control register divr0 r/w pwc (ch.0) ------00 b 83 h (reserved area) 84 h * dividing ratio control register divr1 r/w pwc (ch.1) ------00 b 85 h (reserved area) 86 h * dividing ratio control register divr2 r/w pwc (ch.2) ------00 b 87 h (reserved area)
MB90480/485 series 28 (continued) address register name abbreviated register name read/ write resource name initial value 88 h * bus status register ibsr r i 2 c 00000000 b 89 h * bus control register ibcr r/w 00000000 b 8a h * clock control register iccr r/w --0xxxxx b 8b h * address register iadr r/w -xxxxxxx b 8c h * data register idar r/w xxxxxxxx b 8d h (reserved area) 8e h * pg control status register pgcsr r/w pg 00000--- b 8f h to 9b h (disabled) 9c h dmac status register lower digits dsrl r/w dmac 00000000 b 9d h dmac status register upper digits dsrh r/w dmac 00000000 b 9e h program address detection control status resister pacsr r/w address match detection function 00000000 b 9f h delayed interrupt source general/ cancel register dirr r/w delayed interrupt generator module -------0 b a0 h low-power consumption mode control register lpmcr w, r/w low-power consumption 00011000 b a1 h clock select register ckscr r, r/w low-power consumption 11111100 b a2 h , a3 h (reserved area) a4 h dmac stop status register dssr r/w dmac 00000000 b a5 h automatic ready function select register arsr w external pins 0011 - -00 b a6 h external address output control register hacr w external pins ******** b a7 h bus control signal select register epcr w external pins 1000*10 - b a8 h watchdog timer control register wdtc r, w watchdog timer xxxxx111 b a9 h timebase timer control register tbtc w, r/w timebase timer 1xx00100 b aa h watch timer control register wtc r, r/w watch timer 10001000 b ab h (reserved area) ac h dmac enable register lower digits derl r/w dmac 00000000 b ad h dmac enable register upper digits derh r/w dmac 00000000 b ae h flash memory control status register fmcs w, r/w flash memory interface 000x0000 b af h (disabled) b0 h interrupt control register 00 icr00 w, r/w interrupt controller xxxx0111 b b1 h interrupt control register 01 icr01 w, r/w xxxx0111 b b2 h interrupt control register 02 icr02 w, r/w xxxx0111 b b3 h interrupt control register 03 icr03 w, r/w xxxx0111 b b4 h interrupt control register 04 icr04 w, r/w xxxx0111 b b5 h interrupt control register 05 icr05 w, r/w xxxx0111 b b6 h interrupt control register 06 icr06 w, r/w xxxx0111 b b7 h interrupt control register 07 icr07 w, r/w xxxx0111 b b8 h interrupt control register 08 icr08 w, r/w xxxx0111 b
MB90480/485 series 29 (continued) * : these registers are only for mb90485 series. they are used as the rese rved area on MB90480 series. (continued) address register name abbreviated register name read/ write resource name initial value b9 h interrupt control register 09 icr09 w, r/w interrupt controller xxxx0111 b ba h interrupt control register 10 icr10 w, r/w xxxx0111 b bb h interrupt control register 11 icr11 w, r/w xxxx0111 b bc h interrupt control register 12 icr12 w, r/w xxxx0111 b bd h interrupt control register 13 icr13 w, r/w xxxx0111 b be h interrupt control register 14 icr14 w, r/w xxxx0111 b bf h interrupt control register 15 icr15 w, r/w xxxx0111 b c0 h chip select area mask register 0 cmr0 r/w chip select function 00001111 b c1 h chip select area register 0 car0 r/w 11111111 b c2 h chip select area mask register 1 cmr1 r/w 00001111 b c3 h chip select area register 1 car1 r/w 11111111 b c4 h chip select area mask register 2 cmr2 r/w 00001111 b c5 h chip select area register 2 car2 r/w 11111111 b c6 h chip select area mask register 3 cmr3 r/w 00001111 b c7 h chip select area register 3 car3 r/w 11111111 b c8 h chip select control register cscr r/w ----000* b c9 h chip select active level register calr r/w ----0000 b ca h timer control status register tmcsr r/w 16-bit reload timer 00000000 b cb h ----0000 b cc h 16-bit timer register/ 16-bit reload register tmr/tmrlr r/w xxxxxxxx b cd h ce h (reserved area) cf h pll output control register pllos w low-power consumption ------x0 b d0 h to ff h (external area) 100 h to # h (ram area) 1ff0 h program address detection register 0 (low order address) padr0 r/w address match detection function xxxxxxxx b 1ff1 h program address detection register 0 (middle order address) 1ff2 h program address detection register 0 (high order address) 1ff3 h program address detection register 1 (low order address) padr1 r/w address match detection function xxxxxxxx b 1ff4 h program address detection register 1 (middle order address) 1ff5 h program address detection register 1 (high order address)
MB90480/485 series 30 (continued) descriptions for read/write descriptions for initial value r/w : readable and writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. - : this bit is not used. * : the initial value of this bit is ?1? or ?0?. the value depends on the mode pin (md2, md1 and md0) . + : the initial value of this bit is ?1? or ?0?. the value depends on the ram area of device.
MB90480/485 series 31 interrupt sources, interrupt vectors, and interrupt control registers (continued) interrupt source clear of ei 2 os dmac channel number interrupt vector interrupt control register number address number address reset ? #08 ffffdc h ?? int9 instruction ? #09 ffffd8 h ?? exception ? #10 ffffd4 h ?? int0 (irq0) 0 #11 ffffd0 h icr00 0000b0 h int1 (irq1) #12 ffffcc h int2 (irq2) #13 ffffc8 h icr01 0000b1 h int3 (irq3) #14 ffffc4 h int4 (irq4) #15 ffffc0 h icr02 0000b2 h int5 (irq5) #16 ffffbc h int6 (irq6) #17 ffffb8 h icr03 0000b3 h int7 (irq7) #18 ffffb4 h pwc1 (mb90485 series only) #19 ffffb0 h icr04 0000b4 h pwc2 (mb90485 series only) #20 ffffac h pwc0 (mb90485 series only) 1 #21 ffffa8 h icr05 0000b5 h ppg0/ppg1 counter borrow #22 ffffa4 h ppg2/ppg3 counter borrow #23 ffffa0 h icr06 0000b6 h ppg4/ppg5 counter borrow #24 ffff9c h 8/16-bit up/down counter/ timer (ch.0, ch.1) compare/ underflow/overflow/up/down inversion #25 ffff98 h icr07 0000b7 h input capture (ch.0) load 5 #26 ffff94 h input capture (ch.1) load 6 #27 ffff90 h icr08 0000b8 h output compare (ch.0) match 8 #28 ffff8c h output compare (ch.1) match 9 #29 ffff88 h icr09 0000b9 h output compare (ch.2) match 10 #30 ffff84 h output compare (ch.3) match #31 ffff80 h icr10 0000ba h output compare (ch.4) match #32 ffff7c h output compare (ch.5) match #33 ffff78 h icr11 0000bb h uart sending completed 11 #34 ffff74 h 16-bit free run timer overflow, 16-bit reload timer underflow* 2 12 #35 ffff70 h icr12 0000bc h uart receiving completed 7 #36 ffff6c h sio1 (ch.0) 13 #37 ffff68 h icr13 0000bd h sio2 (ch.1) 14 #38 ffff64 h
MB90480/485 series 32 (continued) : interrupt request flag is not cl eared by the interrupt clear signal. : interrupt request flag is clea red by the interrupt clear signal. : interrupt request flag is cleared by the interrupt clear signal (stop request present) . *1 : the flash write/erase, timebase timer, an d watch timer cannot be used at the same time. *2 : when the 16-bit reload timer underflow interr upt is changed from en able (tmcsr : inte = 1) to disable (tmcsr : inte = 0) , disable the interrupt in the interrupt control register (icr12 : il2 to 0 : 111 b ) , then set the inte bit to 0. note : if there are two interrupt sources for the same inte rrupt number, the resource w ill clear both interrupt request flags at the ei 2 os/ dmac interrupt clear signal. therefore if either of the two sources uses the ei 2 os/ dmac function, the other interrupt function cannot be used. the interrupt request enable bit for the corre- sponding resource should be set to ?0? and interrupt requests from that resource should be handled by software polling. interrupt source clear of ei 2 os dmac channel number interrupt vector interrupt control register number address number address i 2 c interface (mb90485 series only) #39 ffff60 h icr14 0000be h a/d conversion 15 #40 ffff5c h flash write/erase, timebase timer, watch timer * 1 #41 ffff58 h icr15 0000bf h delay interrupt generator module #42 ffff54 h
MB90480/485 series 33 peripheral resources 1. i/o ports the i/o ports perform the functions of either sending data from the cpu to the i/o pins, or loading information from the i/o into the cpu, according to the setting of the corresponding port data register (pdr) . the input/ output direction of each i/o pin can be set in individual bit units by the po rt direction register (ddr) for each i/ o port. the MB90480/485 series has 84 input/output pi ns. the i/o ports are port 0 through port a. (1) port data registers *1 : the r/w indication for i/o ports is somewhat diff erent than r/w access to memory, and involves the following operations. ? input mode read : reads the corresp onding signal pin level. write : writes to the output latch. ? output mode read : reads the value from the data register latch. write : outputs the value to the corresponding signal pin. *2 : the initial value of this bit is ?11xxxxxx b ? on mb90485 series. pdr0 initial value access address : 000000 h undefined r/w * 1 pdr1 address : 000001 h undefined r/w * 1 pdr2 address : 000002 h undefined r/w * 1 pdr3 address : 000003 h undefined r/w * 1 pdr4 address : 000004 h undefined r/w * 1 pdr5 address : 000005 h undefined r/w * 1 pdr6 address : 000006 h undefined r/w * 1 pdr7 address : 000007 h undefined * 2 r/w * 1 pdr8 address : 000008 h undefined r/w * 1 pdr9 address : 000009 h undefined r/w * 1 pdra address : 00000a h undefined r/w * 1 7654 321 0 p06 p07 p05 p04 p03 p02 p01 p00 7654 321 0 p16 p17 p15 p14 p13 p12 p11 p10 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 p36 p37 p35 p34 p33 p32 p31 p30 7654 321 0 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 p56 p57 p55 p54 p53 p52 p51 p50 7654 321 0 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 p76 p77 p75 p74 p73 p72 p71 p70 7654 321 0 7654 321 0 p86 p87 p85 p84 p83 p82 p81 p80 p96 p97 p95 p94 p93 p92 p91 p90 7654 321 0 7654 321 0 ? ??? pa3 pa2 pa1 pa0
MB90480/485 series 34 (2) port direction registers *1 : the value is set to ? ? ? on mb90485 series only. *2 : the initial value of this bit is ?xx000000 b ? on mb90485 series only. ? when a set of pins is functioning as a port, the corresponding signal pins are controlled as follows. 0 : input mode. 1 : output mode. reset to ?0?. notes : ? when any of these registers are accessed using a read- modify-write type instruction (such as a bit set instruction) , the bit specified in the instruction will be set to the indicated valu e. however, the contents of output registers corresponding to any other bits having input settings will be rewritten to the input values of those pins at that time. for this reason, when changing any pin that has been us ed for input to output, first write the desired value to the pdr register before setting the ddr register for output. ? p76, p77 (mb90485 series only) this port has no ddr. to use p77 and p76 as i 2 c pins, set the pdr value to ?1? so that port data remains enabled (to use p77 and p76 for general purposes, disable i 2 c) . the port is an open drain output (with no p-ch) . to use it as an input port, therefore, set the pdr to ?1? to turn off the output transistor and add a pull-up resistor to the external output. ddr0 initial value access address : 000010 h 00000000 b r/w ddr1 address : 000011 h 00000000 b r/w ddr2 address : 000012 h 00000000 b r/w ddr3 address : 000013 h 00000000 b r/w ddr4 address : 000014 h 00000000 b r/w ddr5 address : 000015 h 00000000 b r/w ddr6 address : 000016 h 00000000 b r/w ddr7 address : 000017 h 00000000 b * 2 r/w ddr8 address : 000018 h 00000000 b r/w ddr9 address : 000019 h 00000000 b r/w ddra address : 00001a h ----0000 b r/w 7654 3 21 0 d06 d07 d05 d04 d0 3 d02 d01 d00 d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 7654 321 0 d26 d27 d25 d24 d23 d22 d21 d20 7654 321 0 d36 d37 d35 d34 d33 d32 d31 d30 7654 321 0 d46 d47 d45 d44 d43 d42 d41 d40 7654 321 0 d56 d57 d55 d54 d53 d52 d51 d50 7654 321 0 d66 d67 d65 d64 d63 d62 d61 d60 7654 321 0 d75 d74 d73 d72 d71 d70 d77* 1 d76* 1 7654 321 0 d86 d87 d85 d84 d83 d82 d81 d80 7654 321 0 d96 d97 d95 d94 d93 d92 d91 d90 7654 321 0 ? ??? da3 da2 da1 da0
MB90480/485 series 35 (3) port input resistance registers these registers control the use of pull-up resistance in input mode. 0 : no pull-up resistance in input mode. 1 : with pull-up resistance in input mode. in output mode, these registers have no function (no pull-up resistance) . input/output mode settings are controlled by the setting of port direction (ddr) registers. in case of a stop (spl = 1) , no pull-up resistance is applied (high imp edance) . using of this function is prohibited when an external bus is used. do not write to these registers. (4) port output pin registers *1 : the value is set to ? ? ? on mb90485 series only. *2 : the initial value of this bit is ?xx000000 b ? on mb90485 series only. these registers control open dr ain settings in output mode. 0 : standard output port functions in output mode. 1 : open drain output port in output mode. in input mode, these registers have no function (hi-z ou tput) . input/output mode sett ings are controlled by the setting of port direction (ddr) registers. using of this function is prohibited when an external bus is used. do not write to these registers. (5) analog input enable register this register controls the port 6 pins as follows. 0 : port input/output mode. 1 : analog input mode. the default value at reset is all ?1?. (6) up/down timer input enable register this register controls the port 3 pins as follows. 0 : port input mode. 1 : up/down timer input mode.the default value at reset is ?0?. rdr0 initial value access address : 00001c h 00000000 b r/w rdr1 address : 00001d h 00000000 b r/w 7654 321 0 rd06 rd07 rd05 rd04 rd03 rd02 rd01 rd00 7654 321 0 rd16 rd17 rd15 rd14 rd13 rd12 rd11 rd10 odr7 initial value access address : 00001e h 00000000 b * 2 r/w odr4 address : 00001b h 00000000 b r/w 7654 321 0 od75 od74 od73 od72 od71 od70 od76* 1 od77* 1 7654 321 0 od46 od47 od45 od44 od43 od42 od41 od40 ader initial value access address : 00001f h 11111111 b r/w 7654 321 0 ade6 ade7 ade5 ade4 ade3 ade2 ade1 ade0 uder initial value access address : 00000b h xx000000 b r/w 7654 321 0 ? ? ude5 ude4 ude3 ude2 ude1 ude0
MB90480/485 series 36 2. uart the uart is a serial i/o port for asynchronous (sta rt-stop synchronized) communication as well as clk synchronized communication. full duplex double buffer transfer modes : asynchronous (start-s top synchronized) , or clk synchron ized (no start bit or stop bit) . multi-processor mode supported. embedded proprietary baud rate generator asynchronous : 76923/38461/19230/9615/500 k/250 kbps clk synchronized : 16 m/8 m/4 m/2 m/1 m/500 kbps external clock setting available, allows use of any desired baud rate. can use internal clock feed from ppg1. data length : 7-bit (asynchronous normal mode only) or 8-bit. master/slave type communication func tions (in multi-processor mode) . error detection functions (parity, framing, overrun) transfer signals are nrz encoded. dmac supported (for receiving/sending)
MB90480/485 series 37 (1) register list serial mode register (smr) serial control register (scr) serial i/o register (sidr/sodr) serial status register (ssr) communication prescaler control register (cdcr) 000020 h initial value 000021 h initial value 000022 h initial value 000023 h initial value 000025 h initial value smr ? cdcr scr 15 0 sidr (r)/sodr (w) ssr 87 8 bits 8 bits r/w 0 r/w 0 r/w 0 r/w 0 r/w x r/w 0 r/w 0 7654 3210 md0 r/w 0 md1 cs2 cs1 cs0 scke soe reserved r/w 0 r/w 0 r/w 0 r/w 0 w 1 r/w 0 r/w 0 15 14 13 12 11 10 9 8 p r/w 0 pen sbl cl a/d rec rxe txe r/w x r/w x r/w x r/w x r/w x r/w x r/w x 7654 3210 d6 r/w x d7 d5 d4 d3 d2 d1 d0 r 0 r 0 r 0 r 1 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ore r 0 pe fre rdrf tdre bds rie tie r/w 0 ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 srst r/w 0 md ?? div3 div2 div1 div0
MB90480/485 series 38 (2) block diagram md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre bds rie tie f 2 mc-16lx bus sidr sodr sot0 sck0 sin0 control signal ppg1 (internal connection) external clock clock select circuit receiving status decision circuit dmac receiving error generation circuit (to cpu) receiving clock receiving control circuit start bit detect circuit receive bit counter receiving parity counter receiving shifter receiving control circuit sending clock receiving interrupt (to cpu) sending interrupt (to cpu) sending control circuit send start circuit send bit counter send parity counter sending shifter sending start smr control signal scr ssr proprietary baud rate generator
MB90480/485 series 39 3. expanded i/o serial interface the expanded i/o serial interface is an 8-bit 1-channel serial i/o interface for clock synchronized data transfer. a selection of lsb-first or msb-first data transfer is provided. there are two serial i/o operation modes. (1) register list internal shift clock mode : data transfer is synchronized with the internal clock signal. external shift clock mode : data transfer is synchroni zed with a clock signal input from the external clock signal pin (sck) . in this mode the general-purpose port that shares the external clock signal pin (sck) can be used for tr ansfer according to cpu instructions. serial mode control status register 0/1 (smcs0, smcs1) serial data register 0/1 (sdr0, sdr1) communication prescaler control register 0/1 (sdcr0, sdcr1) initial value address : 000027 h 00002b h 00000010 b address : 000026 h 00002a h ----0000 b address : 000028 h 00002c h xxxxxxxx b address : 000029 h 00002d h 0---0000 b 15 14 13 12 11 10 9 8 smd1 smd2 smd0 sie sir busy stop strt r/w r/w r/w r/w r/w r r/w r/w 7654 3 21 0 ? ??? mode bd ss oe s coe r/w r/w r/w r/w ? ??? 7654 321 0 d6 d7 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w ??? r/w r/w r/w r/w 15 14 13 12 11 10 9 8 ? r/w md ?? div3 div2 div1 div0
MB90480/485 series 40 (2) block diagram sin1, sin2 sot1, sot2 sck1, sck2 smd2 smd1 smd0 sie sir busy stop strt mode bds 21 0 soe scoe (msb first) d0 to d7 d7 to d0 (lsb first) sdr (serial data register) internal clock internal data bus transfer direction selection read write control circuit shift clock counter interrupt request internal data bus initial value
MB90480/485 series 41 4. 8/10-bit a/d converter the a/d converter converts analog i nput voltage to digital values, and provides the following features. conversion time : minimum 3.68 s per channel (92 machine cycles at 25 mhz mach ine clock, including sampling time) sampling time : minimum 1.92 s per channel (48 machine cycles at 25 mhz machine clock) rc sequential comparison conversion method, with sample & hold circuit. 8-bit or 10-bit resolution analog input selection of 8 channels single conversion mode : conversion from one selected channel. scan conversion mode : conversion from multiple c onsecutive channels, programmable selection of up to 8 channels. continuous conversion mode : repeat ed conversion of specified channels. stop conversion mode : conversion from one channel followed by a pause until the next activation allows to synchronize with conversion start. at the end of a/d conversion, an a/d conversion comple ted interrupt request can be generated to the cpu. the interrupt can be used activate the dmac in order to transfer the results of a/d conversion to memory for efficient continuous processing. the starting factor conversion may be selected from soft ware, external trigger (falling edge) , or timer (rising edge) . (1) register list adcs2, adcs1 (control status register) adcr2, adcr1 (data register) adcs1 address : 000046 h initial value bit attributes adcs2 address : 000047 h initial value bit attributes adcr1 address : 000048 h initial value bit attributes adcr2 address : 000049 h initial value bit attributes 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 7654 3210 md0 0 r/w md1 ans2 ans1 ans0 ane2 ane1 ane0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 w 0 r/w 15 14 13 12 11 10 9 8 int 0 r/w busy inte paus sts1 sts0 strt reserved x r x r x r x r x r x r x r 7654 3210 d6 x r d7 d5 d4 d3 d2 d1 d0 0 w 0 w 0 w 0 w x r x r x r 15 14 13 12 11 10 9 8 st1 0 w s10 st0 ct1 ct0 ? d9 d8
MB90480/485 series 42 (2) block diagram mp adtg an0 an1 an2 an3 an4 an5 an6 an7 adcr1, adcr2 adcs1, adcs2 av cc avrh av ss input circuit d/a converter sequential comparison register data registers a/d control register 1 a/d control register 2 prescaler operation clock trigger activation timer activation decoder comparator sample & hold circuit timer (ppg1 output) data bus
MB90480/485 series 43 5. 8/16-bit ppg the 8/16-bit ppg is an 8-bit reload timer module that produces a ppg output using a pulse from the timer operation. hardware resources include 6 8-bit down counters, 12 8-bit reload timers, 3 16-bit control registers, 6 external pulse output pins, and 6 interrupt outputs. note that MB90480/485 series has six channels for 8-bit ppg use, which can also be combined as ppg0 + ppg1, ppg2 + ppg3, and ppg4 + ppg5 to operate as a three-channel 16-bit ppg. the following is a summary of functions. 8-bit ppg output 6-channel independent mode : provi des ppg output operation on six independent channels. 16-bit ppg output operation mode : provides 16-bit ppg output on three channels. the six original channels are used in combination as ppg0 + ppg1, ppg2 + ppg3, and ppg4 + ppg5. 8 + 8-bit ppg output operation mode : output from ppg0 (ppg2/ppg4) is used as clock input to ppg1 (ppg3/ ppg5) to provide to 8-bit ppg output at any desired period length. ppg output operation : produces pulse waves at any desired period and duty ratio. the ppg module can also be used with external circuits as a d/a converter. (1) register list ppgc0/ppgc2/ppgc4 (ppg0/ppg2/ppg4 operation mode control register) ppgc1/ppgc3/ppgc5 (ppg1/ppg3/ppg5 operation mode control register) ppg01/ppg23/ppg45 (ppg0 to ppg 5 output control register) ppll0 to ppll5 (reload register l) pplh0 to pplh5 (reload register h) 00003a h 00003c h 00003e h read/write initial value 00003b h 00003d h 00003f h read/write initial value 000040 h 000042 h 000044 h read/write initial value 00002e h 000030 h 000032 h 000034 h 000036 h 000038 h read/write initial value 00002f h 000031 h 000033 h 000035 h 000037 h 000039 h read/write initial value ? x r/w 0 r/w 0 r/w 0 ? x ? x ? 1 7654 3210 ? r/w 0 pen0 pe00 pie0 puf0 ?? reserved ? x r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 ? 1 15 14 13 12 11 10 9 8 ? r/w 0 pen1 pe10 pie1 puf1 md1 md0 reserved r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 7654 3210 pcs1 r/w 0 pcs2 pcs0 pcm2 pcm1 pcm0 reserved reserved r/w x r/w x r/w x r/w x r/w x r/w x r/w x 7654 3210 d06 r/w x d07 d05 d04 d03 d02 d01 d00 r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 d14 r/w x d15 d13 d12 d11 d10 d09 d08
MB90480/485 series 44 (2) block diagram 8-bit ppg ch.0/2/4 block diagram s r q prlbh prll prll ppg0/2/4 pen0 irq pie0 puf0 peripheral clock 16 peripheral clock 8 peripheral clock 4 peripheral clock 2 peripheral clock count clock select timebase counter output main clock 512 pcnt (down counter) ?l?/?h? selector ppg0/2/4 output enable a/d converter ppg0/2/4 output latch ch.1/3/5 borrow ?l? data bus ?h? data bus ppgc0 (operation mode control) ?l?/?h? select
MB90480/485 series 45 8-bit ppg ch.1/3/5 block diagram s r q prlbh prll prll ppg1/3/5 uart0 pen1 irq pie1 puf1 peripheral clock 16 peripheral clock 8 peripheral clock 4 peripheral clock 2 peripheral clock count clock select timebase counter output main clock 512 pcnt (down counter) ?l?/?h? selector ppg1/3/5 output enable ppg1/3/5 output latch ?l? data bus ?h? data bus ppgc1 (operation mode control) ?l?/?h? select
MB90480/485 series 46 6. 8/16-bit up/down counter/timer 8/16-bit up/down counter/timer consists of up/down counter/timer circuits including six event input pins, two 8-bit up/down counters, two 8-bit reload/compare regi sters, as well as the related control circuits. (1) principal functions 8-bit count register enables counting in the range 0 to 256. (in 16-bit 1 mode, counting is enabl ed in the range 0 to 65535) count clock selection provides four count modes. in timer mode, there is a choice of two internal count clock signals. in up/down count mode, there is a choice of trigger edge detection for the input signal from external pins. in phase differential count mode, to handle encoder c ounting for motors, the encoder a-phase, b-phase, and z-phase are each input, enabling easy and highly accurate counting of angle of rotation, speed of rotation, etc. the zin pin provides a selection of two functions. a compare function and reload function are provided, eac h for use separately or in combination. both functions can be activated together for up/dow n counting in any desired bandwidth. individual control over interrupts at comp are, reload (underflow) and overflow events. count direction flag enables identificati on of the last previous count direction. interrupt generated when count direction changes. count modes timer mode up/down count mode phase differential down count mode ( 2) phase differential down count mode ( 8) count clock 125 ns (8 mhz : 2) (at 16 mhz operation) 0.5 s (2 mhz : 8) edge detection falling edge detection rising edge detection both rising/falling edge detection edge detection disabled zin pin counter clear function gate functions compare/reload function compare function (output interrupt at compare events) compare function (output interrupt and clear counter at compare events) reload function (output interrupt and reload at underflow events) compare/reload function (output interrupt and cl ear counter at compare events, output interrupt and reload at underflow events) compare/reload disabled
MB90480/485 series 47 (2) register list ccrh0 (counter control register high ch.0) ccrh1 (counter control register high ch.1) ccrl0/1 (counter control register low ch.0/ch.1) csr0/1 (counter status register ch.0/ch.1) udcr0/1 (up down count register ch.0/ch.1) rcr0/1 (reload/compare register ch.0/ch.1) initial value address : 00006d h 00000000 b initial value address : 000071 h -0000000 b address address : 00006c h : 000070 h initial value 0x00x000 b address address : 000072 h : 000074 h initial value 00000000 b initial value address : 000069 h 00000000 b initial value address : 000068 h 00000000 b initial value address : 00006b h 00000000 b initial value address : 00006a h 00000000 b rcr0 udcr0 udcr1 rcr1 15 0 ccrl0 csr0 ccrh0 ccrl1 csr1 ccrh1 87 8-bit 8-bit reserved area reserved area 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w cdcf m16e cfie clks cms1 cms0 ces1 ces0 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w cdcf ? cfie clks cms1 cms0 ces1 ces0 7654 321 0 r/w w r/w r/w w r/w r/w r/w ctut udms ucre rlde udcc cgsc cge1 cge0 7654 321 0 r/w r/w r/w r/w r/w r/w r r cite cstr udie cmpf ovff udff udf1 udf0 15 14 13 12 11 10 9 8 rrrr rrr r d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 rrrr rrr r d06 d07 d05 d04 d03 d02 d01 d00 15 14 13 12 11 10 9 8 wwww www w d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 wwww www w d06 d07 d05 d04 d03 d02 d01 d00
MB90480/485 series 48 (3) block diagram cge1 cge0 cg s c c a rry cm s 1cm s 0 udm s ce s 1ce s 0 cite udie udf1 udf0 cdcf cfie ctut ucre rlde udcc cmpf udff ovff clk s c s tr 8 - b it 8 - b it ain0 bin0 zin0 udcr0 (up/down co u nt regi s ter 0) edge/level detection relo a d control rcr0 (relo a d/ comp a re regi s ter 0) up/down count clock selection prescaler data bus counter clear count clock interrupt output
MB90480/485 series 49 7. dtp/external interrupt the dtp (data transfer peripheral) is a peripheral block that interfaces external peripherals to the f 2 mc-16lx cpu. the dtp receives dma and interrupt processi ng requests from external peripherals and passes the requests to the f 2 mc-16lx cpu to activate the extended intelligent dmac or interrupt processing. (1) detailed register descriptions (2) block diagram interrupt/dtp enable register (enir : enable interrupt request register) interrupt/dtp source regi ster (eirr : external interrupt request register) interrupt level setting register (elvr : external level register) enir initial value address : 00000c h 00000000 b eirr initial value address : 00000d h xxxxxxxx b initial value address : 00000e h 00000000 b initial value address : 00000f h 00000000 b 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w en6 en7 en5 en4 en3 en2 en1 en0 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w er6 er7 er5 er4 er3 er2 er1 er0 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w la3 lb3 lb2 la2 lb1 la1 lb0 la0 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w la7 lb7 lb6 la6 lb5 la5 lb4 la4 4 4 4 8 4 f 2 mc-16 bus interrupt/dtp enable register gate source f/f edge detection circuit request input interrupt/dtp source register interrupt level setting register
MB90480/485 series 50 8. 16-bit input/output timer the 16-bit input/output timer module is composed of one 16-bit free run timer, six output compare and two input capture modules. these functions ca n be used to output six independent wa veforms based on the 16-bit free run timer, enabling input pulse width measurem ent and external clock frequency measurement. register list 16-bit free run timer 16-bit output compare 16-bit input capture cpclr 15 0 000066/67 h 000062/63 h 000064/65 h tcdt tccs compare-clear register timer counter data register control status register occp0 to occp5 15 0 ocs0/2/4 ocs1/3/5 00004a, 4c, 4e, 50, 52, 54 h 00004b, 4d, 4f, 51, 53, 55 h 000056, 58, 5a h 000057, 59, 5b h output compare register output compare control registers ipcp0, ipcp1 15 0 ic s 01 00005c, 5e h 00005d, 5f h 000060 h input capture data register input capture control status register
MB90480/485 series 51 block diagram tq tq tq tq out0 out1 out2 out3 tq tq out4 out5 in0 in1 bus 16-bit free run timer output compare 0 output compare 1 output compare 2 output compare 3 control logic interrupt 16-bit timer compare register 0 clear compare register 1 compare register 2 compare register 3 capture data register 0 capture data register 1 to each block edge selection edge selection input capture 0 input capture 1 output compare 5 output compare 4 compare register 5 compare register 4
MB90480/485 series 52 (1) 16-bit free run timer the 16-bit free run timer is composed of a 16-bit up-down counter and c ontrol status register. the counter value of this timer is used as the base timer for the input capture and output compare. the counter operation provides a choice of eight clock types. a counter overflow in terrupt can be produced. a mode setting is available to initialize the counte r value whenever the output compare value matches the value in the compare clear register. register list compare clear register (cpclr) timer counter data register (tcdt) timer control status register (tccs) initial value 000067 h xxxxxxxx b initial value 000066 h xxxxxxxx b initial value 000063 h 00000000 b initial value 000062 h 00000000 b initial value 000065 h 0--00000 b initial value 000064 h 00000000 b 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w cl14 cl15 cl13 cl12 cl11 cl10 cl09 cl08 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w cl06 cl07 cl05 cl04 cl03 cl02 cl01 cl00 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w t14 t15 t13 t12 t11 t10 t09 t08 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w t06 t07 t05 t04 t03 t02 t01 t00 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w ? ecke ? msi2 msi1 msi0 iclr icre 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w ivfe ivf stop mode sclr clk2 clk1 clk0
MB90480/485 series 53 block diagram ivf ivfe s top mode s clr clk1 clk0 iclr m s i2 to m s i0 icre clk2 comp a re circ u it pre s c a ler bus interrupt request a/d activation 16-bit free run timer count value output t15 to t00 clock interrupt request 16-bit compare clear register
MB90480/485 series 54 (2) output compare the output compare module is compos ed of a 16-bit compare register, compare output pin unit, and control register. when the value in the compare register in this module matches the 16-bit free run timer, the pin output levels can be inverted and an interrupt generated. there are six compare registers in all, each operating independently. a setting is available to allow two compare registers to be used to control output. interrupts can be set in terms of compare match events. register list output compare registers (occp0 to occp5) output control registers (ocs1/ocs3/ocs5) output control registers (ocs0/ocs2/ocs4) initial value 00004b h 00004d h 00004f h 000051 h 000053 h 000055 h 00000000 b initial value 00004a h 00004c h 00004e h 000050 h 000052 h 000054 h 00000000 b initial value 000057 h 000059 h 00005b h ---00000 b initial values 000056 h 000058 h 00005a h 0000--00 b 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w c14 c15 c13 c12 c11 c10 c09 c08 7654 321 r/w r/w r/w r/w r/w r/w r/w r/w c06 c07 c05 c04 c03 c02 c01 c00 0 15 14 13 12 11 10 9 8 ??? r/w r/w r/w r/w r/w ? ?? cmod ote1 ote0 otd1 otd0 7654 321 0 r/w r/w r/w r/w ?? r/w r/w icp0 icpic ice1 ice0 ?? cst1 cst0
MB90480/485 series 55 block diagram icp1 icp0 ice0 ice0 tq tq cmod ote1 ote0 out0 (2) (4) out1 (3) (5) bus 16-bit timer counter value (t15 to t00) compare control compare register 0 (2, 4) 16-bit timer counter value (t15 to t00) compare control compare register 1 (3, 5) control unit individual control blocks compare 1 (3) (5) interrupt compare 0 (2) (4) interrupt
MB90480/485 series 56 (3) input capture the input capture module performs the functions of detecting the rising edge, falling edge, or both edges of signal input from external circuits, and saving the 16-bit free run timer value at that moment to a register. an interrupt can also be generated at the instant of edge detection. the input capture module cons ists of input capture registers and a co ntrol register. each input capture module has its own external input pin. selection of three types of valid edge for external input signals. rising edge, falling edge, both edges. an interrupt can be generated when a valid edge is detected in the external input signal. register list block diagram input capture data register (ipcp0, ipcp1) input capture control status register (ics01) initial value 00005d h 00005f h xxxxxxxx b initial value 00005c h 00005e h xxxxxxxx b initial value 000060 h 00000000 b 15 14 13 12 11 10 9 8 rrrr rrr r cp14 cp15 cp13 cp12 cp11 cp10 cp09 cp08 7654 321 0 rrrr rrr r cp06 cp07 cp05 cp04 cp03 cp02 cp01 cp00 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w icp0 icp1 ice1 ice0 eg11 eg10 eg01 eg00 in0 eg11 eg10 eg01 eg00 icp1 icp0 ice1 ice0 in1 bus capture data register 0 16-bit timer counter value (t15 to t00) capture data register 1 edge detection edge detection interrupt interrupt
MB90480/485 series 57 9. i 2 c interface (mb90485 series only) the i 2 c interface is a serial i/o port supporting the inter ic bus. serves as a master/slave device on the i 2 c bus. the i 2 c interface has the following functions. ? master/slave transmit/receive ? arbitration function ? clock synchronization ? slave address/general call address detection function ? forwarding direction detection function ? start condition repeated generation and detection ? bus error detection function (1) register list bus status register (ibsr) bus control register (ibcr) clock control register (iccr) address register (iadr) data register (idar) initial value 000088 h 00000000 b initial value 000089 h 00000000 b initial value 00008a h --0xxxxx b initial value 00008b h -xxxxxxx b initial value 00008c h xxxxxxxx b 765 43210 bb rsc al lrb trx aas gca fbt rrr rrrrr 15 14 13 12 11 10 9 8 ber beie scc mss ack gcaa inte int r/w r/w r/w r/w r/w r/w r/w r/w 765 43210 en cs4 cs3 cs2 cs1 cs0 r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 a6 a5 a4 a3 a2 a1 a0 r/w r/w r/w r/w r/w r/w r/w 765 43210 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w
MB90480/485 series 58 (2) block diagram iccr c s 4 c s3 c s 2 c s 1 c s 0 ib s r iccr en bb r s c lrb trx fbt al l as t bit 56 7 8 24 8 16 3 26412 8 256 s ync fir s t byte s cl s da irq ibcr ibcr s cc m ss ack gcaa ib s r aa s gca ber beie inte int idar iadr i 2 c en ab le peripher a l clock clock s election 1 clock dividing 1 clock dividing 2 clock s election 2 s hift clock gener a tion ch a nge timing of s hift clock edge s t a rt/ s top condition detection b us bus y repe a t s t a rt tr a n s mi ss ion/ reception error ar b itr a tion lo s t detection interr u pt re qu e s t end s t a rt m as ter ack en ab le gc-ack en ab le s t a rt/ s top condition detection s l a ve glo ba l c a ll s l a ve a ddre ss comp a ri s on f 2 mc-16lx b us
MB90480/485 series 59 10. 16-bit reload timer the 16-bit reload timer provides a choice of functions, including internal clock signals that count down in synchronization with three types of in ternal clock, as well as an event coun t mode that counts down at specified edge detection events in pulse signals input from extern al pins. this timer defines an underflow as a change in count value from 0000 h to ffff h . thus an underflow will occur when counting from the value ?reload register setting value + 1?. the choice of counting operations includes re load mode, in which the count setting values is reloaded and counting continues following an underflow event, and one-shot mode, in which an underflow event causes counting to stop. an interrupt can be generated at counter underflow, and the timer is dtc compatible. (1) register list tmcsr (timer control status register) timer control status register (high) (tmcsr) timer control status register (low) (tmcsr) 16-bit timer register/16-bit reload register tmr/tmrlr (high) tmr/tmrlr (low) 0000cb h read/write initial value 0000ca h read/write initial value 0000cd h read/write initial value 0000cc h read/write initial value ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ??? csl1 csl0 mod2 mod1 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 7654 3210 oute r/w 0 mod0 outl reld inte uf cnte trg r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 d14 r/w x d15 d13 d12 d11 d10 d09 d08 r/w x r/w x r/w x r/w x r/w x r/w x r/w x 7654 3210 d06 r/w x d07 d05 d04 d03 d02 d01 d00
MB90480/485 series 60 (2) block diagram tmrlr tmr en oute reld outl clk clk uf 3 3 2 16- b it relo a d regi s ter 16- b it timer regi s ter (down co u nter) relo a d control circ u it clock s elector timer control s t a t us regi s ter (tmc s r) oper a tion control circ u it internal data bus count clock generator circuit machine clock prescaler valid clock detection circuit gate input clear pin (tin0) input control circuit external clock function selection select signal reload signal wait signal output signal generation circuit output signal generation circuit pin (tot0) to a/d converter inverted
MB90480/485 series 61 11. pg timer (mb90485 series only) the pg timer performs pulse output in response to the external input. (1) register list (2) block diagram pg control status register (pgcsr) initial value 00008e h 00000--- b 76543210 pen0 pe1 pe0 pmt1 pmt0 r/w r/w r/w r/w r/w mt00 mt01 extc mt00 o u tp u t l a tch mt01 o u tp u t l a tch control circ u it o u tp u t en ab le
MB90480/485 series 62 12. pwc timer (mb90485 series only) the pwc timer is a 16-bit multifunction up-count timer capab le of measuring the pulse width of the input signal. a total of three channels are provided, each consisting of a 16-bit up-count timer, an input pulse divider & divide ratio control register, a measurement input pin, and a 16-bit control register. these components provide the following functions. timer function : ? capable of generating an interrupt r equest at fixed intervals specified. ? the internal clock used as the reference clock can be selected from among three types. pulse width measurement function : ? measures the time between arbitrary events based on external pulse inputs. ? the internal clock used as the reference clock can be selected from among three types. ? measurement modes - ?h? pulse width ( to ) /?l? pulse width ( to ) - rising cycle ( to ) /falling cycle ( to ) - measurement between edges ( or to or ) ? the 8-bit input divider can be used for division measurement by dividing the input pulse by 22 n (n = 1, 2, 3, 4) . ? an interrupt can be generated upon completion of measurement. ? one-time measurement or fast measurement can be selected.
MB90480/485 series 63 (1) register list pwc control/status register (pwcsr0 to pwcsr2) pwc control/status register (pwcsr0 to pwcsr2) pwc data buffer register (pwcr0 to pwcr2) pwc data buffer register (pwcr0 to pwcr2) dividing ratio control register (divr0 to divr2) 000077 h 00007b h 00007f h initial value 0000000x b 000076 h 00007a h 00007e h initial value 00000000 b 000079 h 00007d h 000081 h initial value 00000000 b 000078 h 00007c h 000080 h initial value 00000000 b 000082 h 000084 h 000086 h initial value ------00 b 15 14 13 12 11 10 9 8 strt stop edir edie ovir ovie err r/w r/w r r/w r/w r/w r reserved 76543210 cks1 cks0 pis1 pis0 s/c mod2 mod1 mod0 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 div1 div0 r/w r/w
MB90480/485 series 64 (2) block diagram 2 2 2 3 err pwcr 16 2 cks1/cks0 16 pis0/pis1 err cks0/ cks1 pwcsr divr 15 pwc0 pwc1 error detection pwcr read internal clock (machine clock/4) reload data transfer overflow 16-bit up count timer clock timer clear count enable input waveform comparator dividing ratio selection overflow interrupt request dividing on/off completion of measurement interrupt request control bit output flag set etc. start of measurement edge start edge selection completion edge selection completion of measurement edge control circuit f 2 mc-16 bus clock divider 8-bit divider edge detection divider clear
MB90480/485 series 65 13. watch timer the watch timer is a 15-bit timer using the sub clock. this circuit can generate interrupts at predetermined intervals. also a setting is available to enable it to be used as the clock source for the watchdog timer. (1) register list (2) block diagram watch timer control register (wtc) 0000aa h read/write initial value r 0 r/w 0 r/w 0 r/w 1 r/w 0 r/w 0 r/w 0 7654 3210 sce r/w 1 wdcs wtie wtof wtr wtc2 wtc1 wtc0 wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 10 2 13 2 14 2 15 sub clock watch counter interval selector interrupt generator circuit watch timer interrupt to watchdog timer watch timer control register (wtc) clear
MB90480/485 series 66 14. watchdog timer the watchdog timer is a 2-bit counter that uses the output from the tim ebase timer or watch timer as a count clock signal, and will reset the cpu if not cleared within a predetermined time interval after it is activated. (1) register list (2) block diagram watchdog timer control register (wdtc) 0000a8 h read/write initial value ? x r x r x r x w 1 w 1 w 1 7654 3210 r x ponr wrst erst srst wte wt1 wt0 reserved ponr wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 1 sclk clr clr 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 4 4 watchdog timer control register (wdtc) watchdog timer watch mode start timebase timer mode start sleep mode start hold status start counter clear control circuit count clock selector 2-bit counter watchdog reset generator circuit clear internal reset generator circuit clr and start time-base counter hclk 2 hclk : oscillator clock sclk : sub clock watch timer control register (wto) wdcs bit clock select register (ckscr) scm bit stop mode start re- served
MB90480/485 series 67 15. timebase timer the timebase timer is an 18-bit free r un counter (timebase counter) that coun ts up in synchronization with the internal count clock signal (base oscillator 2) , and functions as an interval timer with a choice of four types of time intervals. other functions provided by this modul e include timer output for the oscillator stabilization wait period, and operating clock signal feed for ot her timer circuits such as the watchdog timer. (1) register list (2) block diagram timebase timer control register (tbtc) 0000a9 h read/write initial value ? x ? x r/w 0 r/w 0 w 1 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? r/w 1 resv ? tbie tbof tbr tbc1 tbc0 of of of of 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 1 3 2 14 2 15 2 16 2 17 2 1 8 ?? re s v tbie tbof tbr tbc1 tbc0 interv a l timer s elector to ppg timer timebase timer counter hclk 2 to watchdog timer power-on reset counter clear control circuit tbof clear timebase timer control register (tbtc) timebase timer interrupt signal to clock control module oscillator stabilization wait time selector tbof set of : overflow hclk : oscillator clock *1 : switch machine clock from main clock or sub clock to pll clock. *2 : switch machine clock from sub clock to main clock. stop mode start hold status start ckscr : mcs = 1 0* 1 ckscr : scs = 0 1* 2
MB90480/485 series 68 16. clock the clock generator module controls the operation of the internal clock circui ts that serve as the operating clock for the cpu and peripheral devices. this internal clock is referred to as the machine cloc k, and one cycle is referred to as a machine cycle. also, the clock signals from the ba se oscillator are called the oscillator clock, and those from the pll oscillator are called the pll clock. (1) register list clock select register (ckscr) pll output select register (pllos) 0000a1 h read/write initial value 0000cf h read/write initial value r 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 0 r/w 0 15 14 13 12 11 10 9 8 mcm r 1 scm ws1 ws0 scs mcs cs1 cs0 ? ? ? ? ? ? ? ? ? ? w x w 0 15 14 13 12 11 10 9 8 ? ? ? ???? ?? pll2
MB90480/485 series 69 (2) block diagram s cm hclk s clk mcm w s 1w s 0 s c s mc s c s 1c s 0 s tp s lp s pl r s t tmd cg1 cg0 re- s erved 2 2 x0a x1a r s t x0 x1 mclk ??????? pll2 4 2 1024 2 4 4 4 2 pll m u ltiplier circ u it low-power consumption mode control register (lpmcr) interrupt release cpu intermittent operation selec tor pin high-impedance control circuit clock selector sub clock generator circuit pin oscillator stabilization wait period selector clock select register (ckscr) timebase timer pin peripheral clock control circuit internal reset generator circuit standby control circuit pin pin to watchdog timer hclk : oscillator clock mclk : main clock sclk : sub clock standby control circuit cpu clock control circuit pin system clock generator circuit clock generator module machine clock oscillator stabilization wait release pin high-impedance control cpu clock internal reset stop, sleep signals stop signal peripheral clock intermittent cycle selection pll output select register (pllos)
MB90480/485 series 70 (3) clock feed map 4 4 3 x0a x1a x0 hclk mclk uart0 cpu, dmac s clk pclk x1 12 3 4 ppg0, ppg1 ppg2, ppg 3 ppg4, ppg5 tin0 tot0 s ck0, s in0 s ot0 s ck1, s ck2 s ot1, s ot2 out0, out1, out2, in0, in1 an0 to an7, adtg c s 0, c s 1, frck irq0 to irq7 s in1, s in2 ain0, ain1 bin0, bin1 zin0, zin1 c s 2, c s3 out 3 , out4, out5 w a tchdog timer o s cill a tor s t ab iliz a tion w a it control pin pin pin pin pins 4 2 clock selector pll multiplier circuit watch timer timebase timer sub clock generator circuit system clock generator circuit 8/16-bit ppg timer 0 8/16-bit ppg timer 1 8/16-bit ppg timer 2 16-bit reload timer 0 chip select 16-bit output compare 16-bit free run timer 16-bit input capture 10-bit a/d converter pins pins pin pin pins pin pins pins pins pins pins pin pins hclk : oscillator clock mclk : main clock sclk : sub clock pclk : pll clock : machine clock peripheral functions clock generator module pins pin extended i/o serial interface, 2 channels 8/16-bit up/down counter external interrupt
MB90480/485 series 71 17. low-power consumption mode the MB90480/485 series uses operating clock selection and clock operation controls to provide the following cpu operating modes : clock modes (pll clock mode, main clock mode, sub clock mode) cpu intermittent operating modes (pll clock intermittent mode, main clock in termittent mode, sub clock intermittent mode) standby modes (sleep mode, timebase timer mode, stop mode, watch mode) (1) register list low-power consumption mode control register (lpmcr) 0000a0 h read/write initial value w 0 r/w 0 w 1 r/w 1 r/w 0 r/w 0 r/w 0 7654 3210 slp w 0 stp spl rst tmd cg1 cg0 reserved
MB90480/485 series 72 (2) block diagram s cm hclk s clk mcm w s 1w s 0 s c s mc s c s 1c s 0 s tp s lp s pl r s t tmd cg1 cg0 re- s erved 2 2 x0a x1a r s t x0 x1 mclk ??????? pll2 4 2 1024 2 4 4 4 2 low-power consumption mode control register (lpmcr) interrupt release cpu intermittent operating selector pin high-impedance control circuit clock selector sub clock generator circuit pin oscillator stabiliza- tion wait period selector clock select register (ckscr) timebase timer pin peripheral clock control circuit internal reset generator circuit standby control circuit pll multiplier circuit pin pin to watchdog timer hclk : oscillator clock mclk : main clock sclk : sub clock standby control circuit cpu clock control cir c uit pin system clock generator circuit clock generator module machine clock oscillator stabilization wait release pin high-impedance control cpu clock internal reset stop, sleep signals stop signal peripheral clock intermittent cycle selection pll output select register (pllos)
MB90480/485 series 73 (3) status transition chart stp = 1 stp = 1 stp = 1 tmd = 0 tmd = 0 tmd = 0 slp = 1 slp = 1 slp = 1 mcs = 0 mcs = 1 scs = 0 scs = 0 scs = 1 scs = 1 power-on reset power-on main clock mode main sleep mode main timebase timer mode main stop mode main clock oscillator stabilization wait pll clock mode pll sleep mode pll timebase timer mode pll stop mode main clock oscillator stabilization wait sub clock mode sub sleep mode watch mode sub stop mode sub clock oscillator stabilization wait interrupt interrupt interrupt interrupt interrupt interrupt oscillator stabilization wait ends reset external reset, watchdog timer reset, software reset interrupt interrupt interrupt oscillator stabilization wait ends oscillator stabilization wait ends oscillator stabilization wait ends
MB90480/485 series 74 18. external bus pin control circuit the external bus pin control circuit controls the exte rnal bus pins used to expand the cpu address/data bus connections to external circuits. (1) register list (2) block diagram auto ready function select register (arsr) external address output control register (hacr) bus control signal select register (epcr) initial value address : 0000a5 h 0011--00 b initial value address : 0000a6 h ******** b initial value address : 0000a7 h 1000*10- b w ? * : write only : not used : may be either ?1? or ?0? www ?? ww 15 14 13 12 11 10 9 8 ior0 w ior1 hmr1 hmr0 ?? lmr1 lmr0 w w w w www 7654 3210 e22 w e23 e21 e20 e19 e18 e17 e16 wwww ww ? 15 14 13 12 11 10 9 8 rye w cke hde iobs hmbs wre lmbs ? p3 p2 p1 p0 p0 p5 rb p4 p5 access control access control address control data control p0 direction p0 data
MB90480/485 series 75 19. chip select function description the chip select module generates a chip select signals , which are used to facilitate connections to external memory devices. the MB90480/485 series has four chip select output pins, each having a chip select area register setting that specifies the corresponding hardware area and select signal that is output when access to the corresponding extern al address is detected. chip select function features the chip select function uses two 8-bit registers for each output pin. one of these registers (carx) is able to detect memory areas in 64 kbytes unit s by specifying the upper 8-bit of the address for match detection. the other register (cmrx) can be used to expand the detecti on area beyond 64 kbytes by masking bits for match detection. note that during external bus holds, the cs output is set to high impedance. (1) register list chip select area mask register (cmrx) chip select area register (carx) chip select control register (cscr) chip select active level register (calr) 0000c0 h 0000c2 h 0000c4 h 0000c6 h read/write initial value 0000c1 h 0000c3 h 0000c5 h 0000c7 h read/write initial value 0000c8 h read/write initial value 0000c9 h read/write initial value cmr1 cmr0 car0 r/w r/w car1 15 0 cmr 3 cmr2 car2 r/w r/w car 3 c s cr r/w calr 8 7 r/w 0 r/w 0 r/w 0 r/w 1 r/w 1 r/w 1 r/w 1 7654 3210 m6 r/w 0 m7 m5 m4 m3 m2 m1 m0 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 15 14 13 12 11 10 9 8 a6 r/w 1 a7 a5 a4 a3 a2 a1 a0 ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w * 7654 3210 ? ? ? ??? opl3 opl2 opl1 opl0 ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ??? actl3 actl2 actl1 actl0 * : the initial value of this bit is ?1? or ?0?. the value depends on the mode pin (md2, md1 and md0) .
MB90480/485 series 76 (2) block diagram a23 to a16 cmrx carx f 2 mc-16lx bus chip select output pins
MB90480/485 series 77 20. rom mirror function select module the rom mirror function selection module sets the data in rom assigned to ff bank so that the data is read by access to 00 bank. (1) register list (2) block diagram note : do not access rom mirror function selecti on register (romm) on using the area of address 004000 h to 00ffff h (008000 h to 00ffff h ) . ? rom mirror function select register (romm) - : not used initial value address : 00006f h ------+1 b ( + ) : mb90f489b : read only, fixed at ?1? other : selectable, initial value 0 r/w r/w 15 14 13 12 11 10 9 8 ? ????? ms mi ( + ) rom addre ss a re a ff ba nk 00 ba nk rom mirror f u nction s elect f 2 mc-16lx bus
MB90480/485 series 78 21. interrupt controller the interrupt control register is built in interrupt controller, and is supported for all i/ o of interrupt function. this register sets corresponding peripheral interrupt level. (1) register list note : the use of access involving read-modify-write in structions may lead to abnormal operation, and should be avoided. interrupt control registers address : icr01 icr03 icr05 icr07 icr09 icr11 icr13 icr15 0000b1 h 0000b3 h 0000b5 h 0000b7 h 0000b9 h 0000bb h 0000bd h 0000bf h icr01, 03, 05, 07, 09, 11, 13, 15 read/write initial value interrupt control registers address : icr00 icr02 icr04 icr06 icr08 icr10 icr12 icr14 0000b0 h 0000b2 h 0000b4 h 0000b6 h 0000b8 h 0000ba h 0000bc h 0000be h icr00, 02, 04, 06, 08, 10, 12, 14 read/write initial value 15 14 13 12 11 10 9 8 w x w x w x r/w 0 r/w 1 r/w 1 r/w 1 ? w x ??? reserved il2 il1 il0 7654 3210 w x w x w x r/w 0 r/w 1 r/w 1 r/w 1 ? w x ??? reserved il2 il1 il0
MB90480/485 series 79 (2) block diagram il2 il1 il0 3 2 3 3 3 f 2 mc-16lx b us interrupt priority setting interrupt requests (peripheral resources) (cpu) interrupt level
MB90480/485 series 80 22. dmac the dmac is a simplified dma module with functions equivalent to ei 2 os. the dmac has 16 dma data transfer channels, and provides the following functions. automatic data transfer between per ipheral resources (i/o) and memory. cpu program execution stops during dma operation. incremental addressing for transfer sour ce and destination can be turned on/off. dma transfer control from the dmac enable register, dmac stop status register, dmac status register, and descriptor. stop requests from resour ces can stop dma transfer. when dma transfer is completed, the dmac status register sets a flag in the bit for the corresponding channel on which transfer was completed, and outputs a co mpletion interrupt to the interrupt controller. (1) register list dmac enable register initial value derh : 0000ad h 00000000 b dmac enable register initial value derl : 0000ac h 00000000 b dmac stop status register initial value dssr : 0000a4 h 00000000 b dmac status register initial value dsrh : 00009d h 00000000 b dmac status register initial value dsrl : 00009c h 00000000 b r/w r/w 15 14 13 12 11 10 9 8 en14 en15 en13 en12 en11 en10 en9 en8 r/w r/w r/w r/w r/w r/w r/w r/w 7654 3210 en6 en7 en5 en4 en3 en2 en1 en0 r/w r/w r/w r/w r/w r/w r/w r/w 7654 3210 stp6 stp7 stp5 stp4 stp3 stp2 stp1 stp0 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 de14 de15 de13 de12 de11 de10 de9 de8 r/w r/w r/w r/w r/w r/w r/w r/w 7654 3210 de6 de7 de5 de4 de3 de2 de1 de0 r/w r/w r/w r/w r/w r/w
MB90480/485 series 81 (2) block diagram cpu dct bap ioa f 2 mc-16lx b us memory space i/o register dmac descriptor buffer transfer i/o register peripheral function (i/o) dma transfer request if transfer not ended read by der dma controller if transfer is ended interrupt controller ioa : i/o address pointer bap : buffer address pointer der : dmac enable register (enx selection) dct : data counter
MB90480/485 series 82 23. address match detection function when the address is equal to a value set in the address detection register , the instruction code loaded into the cpu is replaced forcibly with the int9 instruction code (01 h ). as a result, when the cpu executes a set instruction, the int9 instruction is executed. processing by the in t#9 interrupt routine allows the program patching function to be implemented. two address detection registers are supported. an interrupt enable bit is prepared for each register. if the value set in the address detection register matches an address and if the interrupt enable bit is set at ?1?, the instruction code loaded into the cpu is replaced forc ibly with the int9 instruction code. (1) register list program address detection register 0 (padr0) 76543210 initial value xxxxxxxx b r/w : readable and writable x : undefined resv : reserved bit address padr0 (low order address) : 001ff0 h r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value xxxxxxxx b address padr0 (middle order address) : 001ff1 h r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value xxxxxxxx b address padr0 (high order address) : 001ff2 h r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value xxxxxxxx b address padr1 (low order address) : 001ff3 h r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value xxxxxxxx b address padr1 (middle order address) : 001ff4 h r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value xxxxxxxx b address padr1 (high order address) : 001ff5 h r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value 00000000 b address 00009e h r/w r/w r/w r/w r/w r/w r/w r/w program address detection register 1 (padr1) program address detection control status register (pacsr) resv resv resv resv ad1e resv ad0e resv
MB90480/485 series 83 (2) block diagram intern a l d a t a bus comp a re address latch enable bit f 2 mc-16lx cpu core address detection register int9 instruction
MB90480/485 series 84 electrical characteristics 1. absolute maximum ratings *1 : this parameter is based on v ss = av ss = 0.0 v. *2 : av cc and avrh must not exceed v cc . also, avrh must not exceed av cc . *3 : v i and v 0 must not exceed v cc + 0.3 v. however, if the maximum current to/from and input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4 : maximum output current is defined as the peak value for one of the corresponding pins. *5 : average output current is defined as the average current flow in a 100 ms interval at one of the corresponding pins. *6 : average total output current is defi ned as the average current flow in a 100 ms interval at all corresponding pins. *7 : ? applicable to pins : p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 to pa3 ? use within recommended operating conditions. ? use at dc voltage (current) . ? the + b signal should always be applied with a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values , either instantaneously or for prolonged periods. (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc 3v ss ? 0.3 v ss + 4.0 v v cc 5v ss ? 0.3 v ss + 7.0 v av cc v ss ? 0.3 v ss + 4.0 v *2 avrh v ss ? 0.3 v ss + 4.0 v *2 input voltage* 1 v i v ss ? 0.3 v ss + 4.0 v *3 v ss ? 0.3 v ss + 7.0 v *3, *8, *9 output voltage* 1 v o v ss ? 0.3 v ss + 4.0 v *3 v ss ? 0.3 v ss + 7.0 v *3, *8, *9 maximum clamp current i clamp ? 2.0 + 2.0 ma *7 total maximum clamp current ? i clamp ?? 20 ma *7 ?l? level maximum output current i ol ? 10 ma *4 ?l? level average output current i olav ? 3ma*5 ?l? level maximum total output current i ol ? 60 ma ?l? level total average output current i olav ? 30 ma *6 ?h? level maximum output current i oh ?? 10 ma *4 ?h? level average output current i ohav ?? 3ma*5 ?h? level maximum total output current i oh ?? 60 ma ?h? level total average output current i ohav ?? 30 ma *6 power consumption p d ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
MB90480/485 series 85 (continued) ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective di ode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller power supp ly is off (not fixed at 0 v) , the power supply is provided from the pins, so t hat incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be su fficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuits: *8 : mb90485 series only p20 to p27, p30 to p37, p40 to p47, p70 to p77 pi ns can be used as 5 v i/f pin on applied 5 v to v cc 5 pin. p76 and p77 is n-ch open drain pin. *9 : as for p76 and p77 (n-ch open drain pin) , even if using at 3 v simplicity (v cc 3 = v cc 5) , the ratings are applied. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r protective diode limiting resistance + b input (0 v to 16 v) input/output equivalent circuits
MB90480/485 series 86 2. recommended operating conditions (v ss = av ss = 0.0 v) * : mb90485 series only p20 to p27, p30 to p37, p40 to p47, p70 to p77 pins can be used as 5 v i/f pin on applied 5 v to v cc 5 pin. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 3 2.7 3.6 v during normal operation 1.8 3.6 v to maintain ram state in stop mode v cc 5 2.7 5.5 v during normal operation* 1.8 5.5 v to maintain ram state in stop mode* ?h? level input voltage v ih 0.7 v cc v cc + 0.3 v all pins other than v ih2 , v ihs , v ihm and v ihx v ih2 0.7 v cc v ss + 5.8 v mb90485 series only p76, p77 pins (n-ch open drain pins) v ihs 0.8 v cc v cc + 0.3 v hysteresis input pins v ihm v cc ? 0.3 v cc + 0.3 v md pin input v ihx 0.8 v cc v cc + 0.3 v x0a pin, x1a pin ?l? level input voltage v il v ss ? 0.3 0.3 v cc v all pins other than v ils , v ilm and v ilx v ils v ss ? 0.3 0.2 v cc v hysteresis input pins v ilm v ss ? 0.3 v ss + 0.3 v md pin input v ilx v ss ? 0.3 0.1 v x0a pin, x1a pin operating temperature t a ? 40 + 85 c
MB90480/485 series 87 3. dc characteristics (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? mb90485 series only ? p40 to p47 and p70 to p77 are n- ch open drain pins with control, which are usually used as cmos. ? p76 and p77 are open drain pins without p-ch. ? for use as a single 3 v power supply products, set v cc = v cc 3 = v cc 5. ? when the device is used with dual power supplie s, p20 to p27, p30 to p37, p40 to p47 and p70 to p77 serve as 5 v pins while t he other pins serve as 3 v i/o pins. parameter symbol pin name condition value unit remarks min typ max ?h? level output voltage v oh all output pins v cc = 2.7 v, i oh = ? 1.6 ma v cc 3 ? 0.3 ?? v v cc = 4.5 v, i oh = ? 4.0 ma v cc 5 ? 0.5 ?? v at using 5 v power supply ?l? level output voltage v ol all output pins v cc = 2.7 v, i ol = 2.0 ma ?? 0.4 v v cc = 4.5 v, i oh = 4.0 ma ?? 0.4 v at using 5 v power supply input leakage current i il all input pins v cc = 3.3 v, v ss < v i < v cc ? 10 ?+ 10 a pull-up resistance r pull ? v cc = 3.0 v, at t a = + 25 c 20 53 200 k ? open drain output current i leak p40 to p47, p70 to p77 ?? 0.1 10 a power supply current i cc ? at v cc = 3.3 v, internal 25 mhz operation, normal operation ? 45 60 ma at v cc = 3.3 v, internal 25 mhz operation, flash programming ? 55 70 ma i ccs ? at v cc = 3.3 v, internal 25 mhz operation, sleep mode ? 17 35 ma i ccl ? at v cc = 3.3 v, external 32 khz, internal 8 khz operation, sub clock operation (t a = + 25 c) ? 15 140 a i cct ? at v cc = 3.3 v, external 32 khz, internal 8 khz operation, watch mode (t a = + 25 c) ? 1.8 40 a i cch ? t a = + 25 c, stop mode, at v cc = 3.3 v ? 0.8 40 a input capacitance c in other than av cc , av ss , v cc , v ss ?? 515pf
MB90480/485 series 88 4. ac characteristics (1) clock timing (v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : be careful of the operating voltage. *2 : duty ratio should be 50 % 3 % . parameter sym- bol pin name condi- tion value unit remarks min typ max clock frequency f ch x0, x1 ? 3 ? 25 mhz external crystal oscillator ? 3 ? 50 external clock input ? 4 ? 25 1 multiplied pll ? 3 ? 12.5 2 multiplied pll ? 3 ? 6.66 3 multiplied pll ? 3 ? 6.25 4 multiplied pll ? 3 ? 4.16 6 multiplied pll ? 3 ? 3.12 8 multiplied pll f cl x0a, x1a ?? 32.768 ? khz clock cycle time t c x0, x1 ? 20 ? 333 ns *1 t cl x0a, x1a ?? 30.5 ? s input clock pulse width p wh p wl x0 ? 5 ?? ns p wlh p wll x0a ?? 15.2 ? s*2 input clock rise, fall time t cr t cf x0 ??? 5 ns with external clock internal operating clock frequency f cp ?? 1.5 ? 25 mhz *1 f cpl ??? 8.192 ? khz internal operating clock cycle time t cp ?? 40.0 ? 666 ns *1 t cpl ??? 122.1 ? s
MB90480/485 series 89 x0, x1 clock timing x0 t c t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a, x1a clock timing x0a t cl t cf t cr 0.8 v cc 0.2 v cc p wlh p wll
MB90480/485 series 90 3.6 2.7 3.0 4 1.5 16 25 16 12 25 8 4 34 8 12.5 16 25 20 32 50 20 6 1.5 9 18 24 5 6 10 40 range of warranted pll operation normal operating range power supply voltage v cc (v) internal clock f cp (mhz) internal operating clock freq uency vs. power supply voltage base oscillator frequency vs. inte rnal operating clock frequency base oscillator clock f ch (mhz) internal clock f cp (mhz) range of warranted pll operation notes: ? for a/d operating frequency, refer to ?5. a/d converter electrical characteristics? ? only at 1 multiplied pll, use with more than f cp = 4 mhz. no multiplied *1 : in setting as 1, 2, 3 and 4 multiplied pll, when the internal clock is used at 20 mhz < f cp 25 mhz, set the pllos register to ?div2 bit = 1? and ?pll2 bit = 1?. [example] when using the base oscillator fr equency of 24 mhz at 1 multiplied pll : ckscr register : cs1 bit = ?0?, cs0 bit = ?0? pllos register : pll2 bit = ?1? [example] when using the base oscillator fr equency of 6 mhz at 3 multiplied pll : ckscr register : cs1 bit = ?1?, cs0 bit = ?0? pllos register : pll2 bit = ?1? *2 : in setting as 2 and 4 multiplied pll, when the internal clock is used at 20 mhz < f cp 25 mhz, the following setting is also enabled. 2 multiplied pll : ckscr register : cs1 bit = ?0?, cs0 bit = ?0? pllos register : pll2 bit = ?1? 4 multiplied pll : ckscr register : cs1 bit = ?0?, cs0 bit = ?1? pllos register : pll2 bit = ?1? *3 : when using in setting as 6 and 8 multiplie d pll, set the pllos register to ?div2 bit = 0? and ?pll2 bit = 1?. [example] when using the base oscillator fr equency of 4 mhz at 6 multiplied pll : ckscr register : cs1 bit = ?1?, cs0 bit = ?0? pllos register : pll2 bit = ?1? [example] when using the base oscillator fr equency of 3 mhz at 8 multiplied pll : ckscr register : cs1 bit = ?1?, cs0 bit = ?1? pllos register : pll2 bit = ?1? 1 * 1 2 * 1, * 2 3 * 1 4 * 1, * 2 6 * 3 8 * 3
MB90480/485 series 91 ac standards are set at the following measurement voltage values. 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc input signal waveform hysteresis input pins output signal waveform output pins pins other than hysteresis input/md input
MB90480/485 series 92 (2) clock output timing (v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. parameter symbol pin name conditions value unit remarks min max cycle time t cyc clk ? t cp * ? ns clk clk t chcl clk v cc = 3.0 v to 3.6 v t cp * / 2 ? 15 t cp * / 2 + 15 ns at f cp = 25 mhz v cc = 2.7 v to 3.3 v t cp * / 2 ? 20 t cp * / 2 + 20 ns at f cp = 16 mhz v cc = 2.7 v to 3.3 v t cp * / 2 ? 64 t cp * / 2 + 64 ns at f cp = 5 mhz clk t cyc 2.4 v 2.4 v 0.8 v t chcl
MB90480/485 series 93 (3) reset input standards (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. *2 : oscillator oscillation time is the time to 90 % of amplitude. for a crystal oscillato r this is on the order of several milliseconds to tens of milliseconds. for a ceramic oscillator, this is several hundred microseconds to several milliseconds. for an external clock signal the value is 0 ms. parameter symbol pin name condi- tions value unit remarks min max reset input time t rstl rst ? 16 t cp * 1 ? ns normal operation oscillator oscillation time* 2 + 4 t cp * 1 ? ms stop mode rst x0 4 t cp t rstl 0.2 vcc 0.2 vcc in stop mode internal operating clock internal reset oscillator oscillation time oscillator stabil ization wait time instruction execution 90 % of amplitude c l condition for measurement of ac standards pin c l : load capacitance applied to pins during testing clk, ale : c l = 30 pf ad15 to ad00 (address data bus) , rd , wr , a23 to a00/d15 to d00 : c l = 30 pf
MB90480/485 series 94 (4) power-on reset standards (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : power rise time requires v cc < 0.2 v. notes: ? the above standards are for the application of a power-on reset. ? within the device, the power-on reset should be app lied by switching the power supply off and on again. note : rapid fluctuations in power supply voltage may tr igger a power-on reset in some cases. as shown below, when changing supply voltage during operation, it is recommended that volt age changes be suppressed and a smooth restart be applied. parameter symbol pin name conditions value unit remarks min max power rise time t r v cc ? 0.05 30 ms * power down time t off v cc 1 ? ms in repeated operation v cc t r t off 2.7 v 0.2 v 0.2 v 0.2 v v cc v ss the slope of voltage increase should be kept within 50 mv/ms. ram data maintenance main power supply voltage sub power supply voltage
MB90480/485 series 95 (5) bus read timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = 0 c to + 70 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. parameter symbol pin name conditions value unit remarks min max ale pulse width t lhll ale ? t cp * / 2 ? 15 ? ns 16 mhz < f cp 25 mhz t cp * / 2 ? 20 ? ns 8 mhz < f cp 16 mhz t cp * / 2 ? 35 ? ns f cp 8 mhz valid address ale time t avll address, ale ? t cp * / 2 ? 17 ? ns t cp * / 2 ? 40 ? ns f cp 8 mhz ale address valid time t llax ale, address ? t cp * / 2 ? 15 ? ns valid address rd time t avrl rd , address ? t cp * ? 25 ? ns valid address valid data input t avdv address, data ? ? 5 t cp * / 2 ? 55 ns ? 5 t cp * / 2 ? 80 ns f cp 8 mhz rd pulse width t rlrh rd ? 3 t cp * / 2 ? 25 ? ns 16 mhz < f cp 25 mhz 3 t cp * / 2 ? 20 ? ns 8 mhz < f cp 16 mhz rd valid data input t rldv rd , data ? ? 3 t cp * / 2 ? 55 ns ? 3 t cp * / 2 ? 80 ns f cp 8 mhz rd data hold time t rhdx rd , data ? 0 ? ns rd ale time t rhlh rd , ale ? t cp * / 2 ? 15 ? ns rd address valid time t rhax address, rd ? t cp * / 2 ? 10 ? ns valid address clk time t avch address, clk ? t cp * / 2 ? 17 ? ns rd clk time t rlch rd , clk ? t cp * / 2 ? 17 ? ns ale rd time t llrl rd , ale ? t cp * / 2 ? 15 ? ns
MB90480/485 series 96 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc clk ale rd a23 to a16 ad15 to ad00 2.4 v t avch t lhll t rhlh t avll t avrl t rldv t rlrh t rhax t rhdx t llax t llrl t rlch t avdv 0.8 v 2.4 v 0.8 v 2.4 v 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc a23 to a00 d15 to d00 t rldv t rhax t rhdx t avdv 0.8 v 2.4 v address read data read data in multiplexed mode in non-multiplexed mode
MB90480/485 series 97 (6) bus write timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = 0 c to + 70 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. parameter sym- bol pin name condi- tion value unit remarks min max valid address wr time t avwl address, wr ? t cp * ? 15 ? ns wr pulse width t wlwh wrl , wrh ? 3 t cp * / 2 ? 25 ? ns 16 mhz < f cp 25 mhz ? 3 t cp * / 2 ? 20 ? ns 8 mhz < f cp 16 mhz valid data output wr time t dvwh data, wr ? 3 t cp * / 2 ? 15 ? ns wr data hold time t whdx wr , data ? 10 ? ns 16 mhz < f cp 25 mhz ? 20 ? ns 8 mhz < f cp 16 mhz ? 30 ? ns f cp 8 mhz wr address valid time t whax wr , address ? t cp * / 2 ? 10 ? ns wr ale time t whlh wr , ale ? t cp * / 2 ? 15 ? ns wr clk time t wlch wr , clk ? t cp * / 2 ? 17 ? ns
MB90480/485 series 98 wr (wrl, wrh) 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v clk ale a23 to a16 ad15 to ad00 t whlh t avwl t dvwh t dvwh t wlwh t whax t whdx t wlch 0.8 v 2.4 v 0.8 v 2.4 v a23 to a00 d15 to d00 t whax t whdx 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v address write data write data in multiplexed mode in non-multiplexed mode
MB90480/485 series 99 (7) ready input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name conditions value unit remarks min max rdy setup time t ryhs rdy ? 35 ? ns ? 70 ? ns at f cp = 8 mhz rdy hold time t ryhh ? 0 ? ns t ryhh 2.4 v 2.4 v 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc clk ale rd/wr t ryhs t ryhs rdy wait inserted (1 cycle) rdy wait not inserted
MB90480/485 series 100 (8) hold timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. note : one or more cycles are required from the time the hrq pin is read until the hak signal changes. (9) uart timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : c l is the load capacitance ap plied to pins for testing. *2 : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. note : the above rating is in clk synchronous mode. parameter symbol pin name conditions value unit remarks min max pin floating hak time t xhal hak ? 30 t cp *ns hak pin valid time t hahv hak t cp *2 t cp *ns parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc ? internal shift clock mode output pins : c l * 1 = 80 pf + 1 ttl 8 t cp * 2 ? ns sck sot delay time t slov ? ? 80 + 80 ns ? 120 + 120 ns f cp = 8 mhz valid sin sck t ivsh ? 100 ? ns 200 ? ns f cp = 8 mhz sck valid sin hold time t shix ? t cp * 2 ? ns serial clock ?h? pulse width t shsl ? external shift clock mode output pins : c l * 1 = 80 pf + 1 ttl 4 t cp * 2 ? ns serial clock ?l? pulse width t slsh ? 4 t cp * 2 ? ns sck sot delay time t slov ? ? 150 ns ? 200 ns f cp = 8 mhz valid sin sck t ivsh ? 60 ? ns 120 ? ns f cp = 8 mhz sck valid sin hold time t shix ? 60 ? ns 120 ? ns f cp = 8 mhz hak t xhal t hahv 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v pins high-z
MB90480/485 series 101 internal shift clock mode external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc s ck s ot s in t s l s h t s h s l t s lov t iv s h t s hix 0.2 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc 2.4 v 0. 8 v 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc
MB90480/485 series 102 (10) extended i/o serial interface timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : c l is the load capacitance ap plied to pins for testing. *2 : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. notes : ? the above rating is in clk synchronous mode. ? values on this table are target values. parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc ? internal shift clock mode output pins : c l * 1 = 80 pf + 1 ttl 8 t cp * 2 ? ns sck sot delay time t slov ? ? 80 + 80 ns ? 120 + 120 ns f cp = 8 mhz valid sin sck t ivsh ? 100 ? ns 200 ? ns f cp = 8 mhz sck valid sin hold time t shix ? t cp * 2 ? ns serial clock ?h? pulse width t shsl ? external shift clock mode output pins : c l * 1 = 80 pf + 1 ttl 4 t cp * 2 ? ns serial clock ?l? pulse width t slsh ? 4 t cp * 2 ? ns sck sot delay time t slov ? ? 150 ns ? 200 ns f cp = 8 mhz valid sin sck t ivsh ? 60 ? ns 120 ? ns f cp = 8 mhz sck valid sin hold time t shix ? 60 ? ns 120 ? ns f cp = 8 mhz
MB90480/485 series 103 internal shift clock mode external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc s ck s ot s in t s l s h t s h s l t s lov t iv s h t s hix 0.2 v cc 0.2 v cc 0. 8 v cc 0. 8 v cc 2.4 v 0. 8 v 0. 8 v cc 0.2 v cc 0. 8 v cc 0.2 v cc
MB90480/485 series 104 (11) timer input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. (12) timer output timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh t tiwl tin0, in0, in1, pwc0 to pwc2 ? 4 t cp * ? ns parameter sym- bol pin name conditions value unit remarks min max clk change time ppg0 to ppg5 change time out0 to out5 change time t to tot0, ppg0 to ppg5, out0 to out5 load conditions 80 pf 30 ? ns 0. 8 v cc tin0 in0, in1 pwc0 to pwc2 0. 8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl 0.7 v cc clk tot0 0.3 v cc 0.7 v cc t to ppg0 to ppg5 out0 to out5
MB90480/485 series 105 (13) i 2 c timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : f cp is internal operation clock frequen cy. refer to ? (1) clock timing?. *2 : r,c : pull-up resistor and lo ad capacitor of the scl and sda lines. *3 : the maximum t hddat only has to be met if the device does not stretch the ?l? width (t low ) of the scl signal. *4 : refer to ? ? note of sda and scl set-up time?. note : v cc = v cc 3 = v cc 5 parameter symbol condition standard-mode unit min max scl clock frequency f scl when power supply voltage of external pull-up resistance is 5.5 v r = 1.3 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistance is 3.6 v r = 1.6 k ? , c = 50 pf* 2 0 100 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? s ?l? width of the scl clock t low 4.7 ? s ?h? width of the scl clock t high 4.0 ? s set-up time (repeated) start condition scl sda t susta 4.7 ? s data hold time scl sda t hddat 0 3.45* 3 s data set-up time sda scl t sudat when power supply voltage of external pull-up resistance is 5.5 v f cp * 1 20 mhz, r = 1.3 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistance is 3.6 v f cp * 1 20 mhz, r = 1.6 k ? , c = 50 pf* 2 250* 4 ? ns when power supply voltage of external pull-up resistance is 5.5 v f cp * 1 > 20 mhz, r = 1.3 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistance is 3.6 v f cp * 1 > 20 mhz, r = 1.6 k ? , c = 50 pf* 2 200* 4 ? ns set-up time for stop condition scl sda t susto when power supply voltage of external pull-up resistance is 5.5 v r = 1.3 k ? , c = 50 pf* 2 when power supply voltage of external pull-up resistance is 3.6 v r = 1.6 k ? , c = 50 pf* 2 4.0 ? s bus free time between a stop and start condition t bus 4.7 ? s
MB90480/485 series 106 note : the rating of the input data se t-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. be sure to adjust the pull-up resistor of sda and scl if the rating of the input dat a set-up time cannot be satisfied. sda scl 6 tcp ? note of sda and scl set-up time input data set-up time sda scl t bus t low f scl t hddat t high t sudat t hdsta t susta t hdsta t susto ? timing definition
MB90480/485 series 107 (14) trigger input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. (15) up-down counter timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. parameter symbol pin name condi- tions value unit remarks min max input pulse width t trgh t trgl adtg, irq0 to irq7 ? 5 t cp * ? ns normal operation 1 ? s stop mode parameter symbol pin name conditions value unit remarks min max ain input ?h? pulse width t ahl ain0, ain1, bin0, bin1 load conditions 80 pf 8 t cp * ? ns ain input ?l? pulse width t all 8 t cp * ? ns bin input ?h? pulse width t bhl 8 t cp * ? ns bin input ?l? pulse width t bll 8 t cp * ? ns ain bin time t aubu 4 t cp * ? ns bin ain time t buad 4 t cp * ? ns ain bin time t adbd 4 t cp * ? ns bin ain time t bdau 4 t cp * ? ns bin ain time t buau 4 t cp * ? ns ain bin time t aubd 4 t cp * ? ns bin ain time t bdad 4 t cp * ? ns ain bin time t adbu 4 t cp * ? ns zin input ?h? pulse width t zhl zin0, zin1 4 t cp * ? ns zin input ?l? pulse width t zll 4 t cp * ? ns 0.8 v cc irq0 to irq7 adtg 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl
MB90480/485 series 108 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc t all t bll t bhl t ahl t aubu t buad t adbd t bdau ain bin 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc t buau t aubd t zhl t zll t bdad t adbu bin ain zin
MB90480/485 series 109 (16) chip select output timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : t cp is internal operating clock cycle time. refer to ? (1) clock timing?. note : due to the configuration of the internal bus, t he chip select output signals are changed simultaneously and therefore may cause the bus conflict conditions. ac cannot be warranted between the ale output signal and the chip select output signal. parameter sym- bol pin name condi- tions value unit remarks min max chip select output valid time rd t svrl cs0 to cs3, rd ? t cp * / 2 ? 7 ? ns chip select output valid time wr t svwl cs0 to cs3, wrh , wrl ? t cp * / 2 ? 7 ? ns rd chip select output valid time t rhsv rd , cs0 to cs3 ? t cp * / 2 ? 17 ? ns wr chip select output valid time t whsv wrh , wrl , cs0 to cs3 ? t cp * / 2 ? 17 ? ns t svrl t svwl t whsv t rhsv 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v rd a23 to a16 cs0 to cs3 d15 to d00 wrh, wrl d15 to d00 read data write data unde- fined
MB90480/485 series 110 5. a/d converter electrical characteristics (v cc = av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, 2.7 v avrh, t a = ? 40 c to + 85 c) *1 : at machine clock frequency of 25 mhz. *2 : cpu stop mode current when a/ d converter is not operating (at v cc = av cc = avrh = 3.0 v) . parameter sym- bol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb linear error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full scale transition voltage v fst an0 to an7 avrh ? 3.5 lsb avrh ? 1.5 lsb avrh + 0.5 lsb mv conversion time ?? 3.68 * 1 ?? s analog port input current i ain an0 to an7 ? 0.1 10 a analog input voltage v ain an0 to an7 av ss ? avrh v reference voltage ? avrh av ss + 2.2 ? av cc v power supply current i a av cc ? 1.4 3.5 ma i ah av cc ?? 5 * 2 a reference voltage supply current i r avrh ? 94 150 a i rh avrh ?? 5 * 2 a offset between channels ? an0 to an7 ?? 4lsb
MB90480/485 series 111 ? about the external impedance of th e analog input and its sampling time a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. to satisfy the a/d conversion precision standard, cons ider the relationship between the external impedance and minimum sampling time and either adjust the regi ster value and operating frequency or decrease the external impedance so that the sampling ti me is longer than the minimum value. if the sampling time cannot be suffici ent, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |avrh ? av ss | becomes smaller, values of relative errors grow larger. note : concerning sampling time, and compare time when 3.6 v av cc 2.7 v, then sampling time : 1.92 s, compare time : 1.1 s settings should ensure that actual values do not go below these values due to operating frequency changes. r c during sampling : on analog input comparator note: the values are reference values. analog input equivalent circuit rc mb90487b 2.5 k ? (max) 31.0 pf (max) mb90f481/f482 1.9 k ? (max) 25.0 pf (max) mb90f488b/f489b 1.9 k ? (max) 25.0 pf (max) mb90f481/f482 mb90f488b/f489b mb90487b 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 mb90f481/f482 mb90f488b/f489b mb90487b 20 18 16 14 12 10 8 6 4 2 0 0123456 8 7 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) minimum sampling time [ s] minimum sampling time [ s] external impedance [k ? ] external impedance [k ? ] ? the relationship between external impedance and minimum sampling time
MB90480/485 series 112 flash memory program/erase characteristics * : the value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . use of the x0/x1, x0a/x1a pins sample use with external clock input parameter conditions value unit remarks min typ max sector erase time t a = + 25 c, v cc = 3.0 v ? 115s excludes 00 h programming prior erasure chip erase time ? 7 ? s excludes 00 h programming prior erasure word (16-bit) programming time ? 16 3600 s excludes system-level overhead program/erase cycle ? 10000 ?? cycle flash memory data hold time average t a = + 85 c 10 ?? year * x1 c3 c4 c2 c1 x0 x0a x1a when used with a crystal oscillator pull-up resistance 1 damping resistance 1 damping resistance 2 internal damping resistance 0 in normal use : internal damping resistance 0 : typ 600 ? consult with the oscillator manufacturer. pull-up resistance 1, damping resistance 1, 2, c1 to c4 x0 x1 open MB90480/485 series
MB90480/485 series 113 example characteristics mb90f482 (continued) v oh ? i oh t a = + 25 c v ol ? i ol t a = + 25 c cmos input characteristics t a = + 25 c hysteresis input characteristics t a = + 25 c 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 ? 1 ? 2 ? 3 ? 4 ? 5 v oh (v) i oh (ma) v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.3 v v cc = 3.6 v v cc = 3.9 v 1800 1600 1400 1200 1000 600 400 200 0 12345 800 v ol (mv) i ol (ma) v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.3 v v cc = 3.6 v v cc = 3.9 v 2.4 2.0 1.8 1.6 1.4 1.2 1.0 0.6 0.4 2.4 2.7 3.0 3.3 3.6 0.8 2.2 v cc (v) v ih v il cmos input (v) 2.4 2.0 1.8 1.6 1.4 1.2 1.0 0.6 0.4 2.4 2.7 3.0 3.3 3.6 0.8 2.2 v cc (v) v ihs v ils hysteresis input (v)
MB90480/485 series 114 (continued) 40 30 20 10 0 50 60 2.4 2.7 3.0 3.3 3.6 3.9 f = 1 mhz f = 2 mhz f = 4 mhz f = 10 mhz f = 16 mhz f = 20 mhz f = 25 mhz v cc (v) i cc ? v cc i cc (ma) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 v cc (v) i cch ( a) i cch ? v cc 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 v cc (v) i cct ( a) i cct ? v cc
MB90480/485 series 115 (continued) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 v cc (v) i a (ma) i a ? v cc 1000 100 10 2.4 2.7 3.0 3.3 3.6 3.9 v cc (v) r (k ? ) r ? v cc
MB90480/485 series 116 (continued) 20 18 16 14 12 10 8 6 4 2 0 2.4 2.7 3.0 3.3 3.6 3.9 f = 1 mhz f = 2 mhz f = 4 mhz f = 10 mhz f = 16 mhz f = 20 mhz f = 25 mhz v cc (v) i ccs ? v cc i ccs (ma) 20 18 16 14 12 10 8 6 4 2 0 2.4 2.7 3.0 3.3 3.6 3.9 v cc (v) i ccl ( a) i ccl ? v cc 250 200 150 100 50 0 2.4 2.7 3.0 3.3 3.6 3.9 v cc (v) i r ( a) i r ? v cc
MB90480/485 series 117 ordering information part number package remarks mb90f481pf mb90f482pf mb90487bpf mb90488bpf mb90f488bpf mb90483cpf mb90f489bpf 100-pin plastic qfp (fpt-100p-m06) mb90f481pfv mb90f482pfv mb90487bpfv mb90488bpfv mb90f488bpfv mb90483cpfv mb90f489bpfv 100-pin plastic lqfp (fpt-100p-m05)
MB90480/485 series 118 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 100-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0.65g code (reference) p-lfqfp100-14 14-0.50 100-pin pl as tic lqfp (fpt-100p-m05) (fpt-100p-m05) c 200 3 fujit s u limited f100007 s -c-4-6 14.000.10(.551.004) s q 16.000.20(.6 3 0.00 8 ) s q 125 26 51 76 50 75 100 0.50(.020) 0.200.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.1450.055 (.0057.0022) 0.0 8 (.00 3 ) "a" index .059 ?.004 +.00 8 ?0.10 +0.20 1.50 (mo u nting height) 0 ? ~ 8 ? 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.25(.010) 0.100.10 (.004.004) det a il s of "a" p a rt ( s t a nd off) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
MB90480/485 series 119 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 100-pin pl as tic qfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 14.00 20.00 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 3 . 3 5 mm max code (reference) p-qfp100-14 20-0.65 100-pin pl as tic qfp (fpt-100p-m06) ( fpt-100p-m06 ) c 2002 fujit s u limited f10000 8s -c-5-5 1 3 0 3 1 50 51 8 0 8 1 100 20.000.20(.7 8 7.00 8 ) 2 3 .900.40(.941.016) 14.000.20 (.551.00 8 ) 17.900.40 (.705.016) index 0.65(.026) 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) "a" 0.170.06 (.007.002) 0.10(.004) det a il s of "a" p a rt (.0 3 5.006) 0. 88 0.15 (.0 3 1.00 8 ) 0. 8 00.20 0.25(.010) 3 .00 +0. 3 5 ?0.20 +.014 ?.00 8 .11 8 (mo u nting height) 0.250.20 (.010.00 8 ) ( s t a nd off) 0~ 8 ? * * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
MB90480/485 series f0611 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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